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| author | Aaron Durbin <adurbin@chromium.org> | 2016-11-10 15:15:35 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-11-12 04:06:33 +0100 |
| commit | 2bebd7bc93e248f5bdf5677d07802eb9e14528b0 (patch) | |
| tree | c7ee105da1c415f33391382a7e4a7dcc051c5d86 /src/include | |
| parent | 2b3e0cdfc4ddefb85e779fa789ba21406a5f76a3 (diff) | |
| download | coreboot-2bebd7bc93e248f5bdf5677d07802eb9e14528b0.tar.xz | |
cpu/x86/mtrr: allow temporary MTRR range during coreboot
Certain platforms have a poorly performing SPI prefetcher so even if
accessing MMIO BIOS once the fetch time can be impacted. Payload
loading is one example where it can be impacted. Therefore, add the
ability for a platform to reconfigure the currently running CPU's
variable MTRR settings for the duration of coreboot's execution.
The function mtrr_use_temp_range() is added which uses the previous
MTRR solution as a basis along with a new range and type to use.
A new solution is calculated with the updated settings and the
original solution is put back prior to exiting coreboot into the OS
or payload.
Using this patch on apollolake reduced depthcharge payload loading
by 75 ms.
BUG=chrome-os-partner:56656,chrome-os-partner:59682
Change-Id: If87ee6f88e0ab0a463eafa35f89a5f7a7ad0fb85
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17371
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/cpu/x86/mtrr.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 79f98905b3..d9f38f57ee 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -45,6 +45,9 @@ #if !defined (__ASSEMBLER__) && !defined(__PRE_RAM__) +#include <stdint.h> +#include <stddef.h> + /* * The MTRR code has some side effects that the callers should be aware for. * 1. The call sequence matters. x86_setup_mtrrs() calls @@ -77,6 +80,10 @@ void x86_setup_fixed_mtrrs(void); /* Set up fixed MTRRs but do not enable them. */ void x86_setup_fixed_mtrrs_no_enable(void); void x86_mtrr_check(void); + +/* Insert a temporary MTRR range for the duration of coreboot's runtime. + * This function needs to be called after the first MTRR solution is derived. */ +void mtrr_use_temp_range(uintptr_t begin, size_t size, int type); #endif #if !defined(__ASSEMBLER__) && defined(__PRE_RAM__) && !defined(__ROMCC__) |