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authorRonald G. Minnich <rminnich@gmail.com>2006-04-10 16:40:19 +0000
committerRonald G. Minnich <rminnich@gmail.com>2006-04-10 16:40:19 +0000
commit45f6c5e3d450053e53a8ff4a687fd0dcaf2d7475 (patch)
tree8cf49ad51549655c749bc7bc8edd98de41bd604e /src/include
parent526b2c429e41bbd177853169deb63c1bf00c70a9 (diff)
downloadcoreboot-45f6c5e3d450053e53a8ff4a687fd0dcaf2d7475.tar.xz
add cpureginit to romcc code.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/include')
-rw-r--r--src/include/cpu/amd/gx2def.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/include/cpu/amd/gx2def.h b/src/include/cpu/amd/gx2def.h
index 9bb4f571f0..5ca14dd92d 100644
--- a/src/include/cpu/amd/gx2def.h
+++ b/src/include/cpu/amd/gx2def.h
@@ -69,11 +69,11 @@
#define GL0_DF 6
#define GL1_GLIU0 1
-#define GL1_GLCP 3
+#define GL1_GLCP 3
#define GL1_PCI 4
#define GL1_FG 5
-#define GL1_VIP 5
-#define GL1_AES 6
+#define GL1_VIP 5
+#define GL1_AES 6
#define MSR_GLIU0 (GL0_GLIU0 << 29) + (1 << 28) /* To get on GeodeLink one bit has to be set */
#define MSR_MC (GL0_MC << 29)