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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-09 09:37:49 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-15 05:31:29 +0000
commit5bc641afebda5fd274ba713add4145651d9bc71d (patch)
tree849f5712a83c5eb895ae3aee24a26509c8a8421b /src/include
parentb3267e002e798e90ca09b11e42ea8949dccde2e7 (diff)
downloadcoreboot-5bc641afebda5fd274ba713add4145651d9bc71d.tar.xz
cpu/intel: Refactor platform_enter_postcar()
There are benefits in placing the postcar_frame structure in .bss and returning control to romstage_main(). Change-Id: I0418a2abc74f749203c587b2763c5f8a5960e4f9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/include')
-rw-r--r--src/include/cpu/intel/romstage.h6
1 files changed, 5 insertions, 1 deletions
diff --git a/src/include/cpu/intel/romstage.h b/src/include/cpu/intel/romstage.h
index 47cd169e6a..328f464ec4 100644
--- a/src/include/cpu/intel/romstage.h
+++ b/src/include/cpu/intel/romstage.h
@@ -5,6 +5,10 @@
void mainboard_romstage_entry(unsigned long bist);
-void platform_enter_postcar(void);
+/* fill_postcar_frame() is called after raminit completes and right before
+ * calling run_postcar_phase(). Implementation should call postcar_frame_add_mtrr()
+ * to tag memory ranges as cacheable to speed up execution of postcar and
+ * early ramstage. */
+void fill_postcar_frame(struct postcar_frame *pcf);
#endif /* _CPU_INTEL_ROMSTAGE_H */