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authorElyes HAOUAS <ehaouas@noos.fr>2020-10-15 12:24:00 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-11-04 09:40:40 +0000
commit5f5fd853ed3eac04990d50571f7c5daf2a028ed8 (patch)
tree65167068e77c18149a7d35e83ec15f514eb64938 /src/include
parentb20aac072144e650dd5ba93bb4bfce1e061732e8 (diff)
downloadcoreboot-5f5fd853ed3eac04990d50571f7c5daf2a028ed8.tar.xz
acpi/acpi.h: Update region spaces
Update operation region spaces according to ACPI Release 6.3 Errata A. Change-Id: I05305c96a2170eaf651d71ac79b67653745108a2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/include')
-rw-r--r--src/include/acpi/acpi.h31
1 files changed, 18 insertions, 13 deletions
diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h
index a9ec07754d..78740fb796 100644
--- a/src/include/acpi/acpi.h
+++ b/src/include/acpi/acpi.h
@@ -99,19 +99,24 @@ typedef struct acpi_gen_regaddr {
u32 addrh; /* Register address, high 32 bits */
} __packed acpi_addr_t;
-#define ACPI_ADDRESS_SPACE_MEMORY 0 /* System memory */
-#define ACPI_ADDRESS_SPACE_IO 1 /* System I/O */
-#define ACPI_ADDRESS_SPACE_PCI 2 /* PCI config space */
-#define ACPI_ADDRESS_SPACE_EC 3 /* Embedded controller */
-#define ACPI_ADDRESS_SPACE_SMBUS 4 /* SMBus */
-#define ACPI_ADDRESS_SPACE_PCC 0x0A /* Platform Comm. Channel */
-#define ACPI_ADDRESS_SPACE_FIXED 0x7f /* Functional fixed hardware */
-#define ACPI_FFIXEDHW_VENDOR_INTEL 1 /* Intel */
-#define ACPI_FFIXEDHW_CLASS_HLT 0 /* C1 Halt */
-#define ACPI_FFIXEDHW_CLASS_IO_HLT 1 /* C1 I/O then Halt */
-#define ACPI_FFIXEDHW_CLASS_MWAIT 2 /* MWAIT Native C-state */
-#define ACPI_FFIXEDHW_FLAG_HW_COORD 1 /* Hardware Coordination bit */
-#define ACPI_FFIXEDHW_FLAG_BM_STS 2 /* BM_STS avoidance bit */
+#define ACPI_ADDRESS_SPACE_MEMORY 0 /* System memory */
+#define ACPI_ADDRESS_SPACE_IO 1 /* System I/O */
+#define ACPI_ADDRESS_SPACE_PCI 2 /* PCI config space */
+#define ACPI_ADDRESS_SPACE_EC 3 /* Embedded controller */
+#define ACPI_ADDRESS_SPACE_SMBUS 4 /* SMBus */
+#define ACPI_ADDRESS_SPACE_CMOS 5 /* SystemCMOS */
+#define ACPI_ADDRESS_SPACE_PCI_BAR_TARGET 6 /* PciBarTarget */
+#define ACPI_ADDRESS_SPACE_IPMI 7 /* IPMI */
+#define ACPI_ADDRESS_SPACE_GENERAL_PURPOSE_IO 8 /* GeneralPurposeIO */
+#define ACPI_ADDRESS_SPACE_GENERIC_SERIAL_BUS 9 /* GenericSerialBus */
+#define ACPI_ADDRESS_SPACE_PCC 0x0A /* Platform Comm. Channel */
+#define ACPI_ADDRESS_SPACE_FIXED 0x7f /* Functional fixed hardware */
+#define ACPI_FFIXEDHW_VENDOR_INTEL 1 /* Intel */
+#define ACPI_FFIXEDHW_CLASS_HLT 0 /* C1 Halt */
+#define ACPI_FFIXEDHW_CLASS_IO_HLT 1 /* C1 I/O then Halt */
+#define ACPI_FFIXEDHW_CLASS_MWAIT 2 /* MWAIT Native C-state */
+#define ACPI_FFIXEDHW_FLAG_HW_COORD 1 /* Hardware Coordination bit */
+#define ACPI_FFIXEDHW_FLAG_BM_STS 2 /* BM_STS avoidance bit */
/* 0x80-0xbf: Reserved */
/* 0xc0-0xff: OEM defined */