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authorJamie Chen <jamie.chen@intel.com>2020-04-16 01:20:29 +0800
committerPatrick Georgi <pgeorgi@google.com>2020-05-13 12:04:03 +0000
commit7adcfde079324b834c9a6370af38e56e34f1c45c (patch)
treed056935c7da7838a3078f13a4df9acd1e7ccacf8 /src/include
parent7d1a4b2584ce61f89f8b4de52880f0a6db96aa94 (diff)
downloadcoreboot-7adcfde079324b834c9a6370af38e56e34f1c45c.tar.xz
lib/spd_bin: add get_spd_sn function
This patch adds the get_spd_sn function. It's for reading SODIMM serial number. In spd_cache implementation it can use to get serial number before reading whole SPD by smbus. BUG=b:146457985 BRANCH=None TEST=Wrote sample code to get the serial number and ran on puff. It can get the serial number correctly. Change-Id: I406bba7cc56debbd9851d430f069e4fb96ec937c Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40414 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include')
-rw-r--r--src/include/spd_bin.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h
index d1ee6f775c..11a0084c70 100644
--- a/src/include/spd_bin.h
+++ b/src/include/spd_bin.h
@@ -21,16 +21,19 @@
#define SPD_DRAM_LPDDR5 0x13
#define SPD_DENSITY_BANKS 4
#define SPD_ADDRESSING 5
+#define SPD_SN_LEN 4
#define DDR3_ORGANIZATION 7
#define DDR3_BUS_DEV_WIDTH 8
#define DDR4_ORGANIZATION 12
#define DDR4_BUS_DEV_WIDTH 13
#define DDR3_SPD_PART_OFF 128
#define DDR3_SPD_PART_LEN 18
+#define DDR3_SPD_SN_OFF 122
#define LPDDR3_SPD_PART_OFF 128
#define LPDDR3_SPD_PART_LEN 18
#define DDR4_SPD_PART_OFF 329
#define DDR4_SPD_PART_LEN 20
+#define DDR4_SPD_SN_OFF 325
struct spd_block {
u8 addr_map[CONFIG_DIMM_MAX]; /* 7 bit I2C addresses */
@@ -45,6 +48,13 @@ int get_spd_cbfs_rdev(struct region_device *spd_rdev, u8 spd_index);
void dump_spd_info(struct spd_block *blk);
void get_spd_smbus(struct spd_block *blk);
+/*
+ * get_spd_sn returns the SODIMM serial number. It only supports DDR3 and DDR4.
+ * return CB_SUCCESS, sn is the serial number and sn=0xffffffff if the dimm is not present.
+ * return CB_ERR, if dram_type is not supported or addr is a zero.
+ */
+enum cb_err get_spd_sn(u8 addr, u32 *sn);
+
/* expects SPD size to be 128 bytes, reads from "spd.bin" in CBFS and
verifies the checksum. Only available if CONFIG_DIMM_SPD_SIZE == 128. */
int read_ddr3_spd_from_cbfs(u8 *buf, int idx);