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authorStefan Reinauer <reinauer@chromium.org>2011-05-10 10:46:41 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-03-09 20:31:45 +0100
commit8907e816265d9821e39bb21333f6212b97e80504 (patch)
tree403b32537792fa1e8e127d8f1f2550e8688ddb01 /src/include
parenta6087d155de715d1268c115c42ab7b0ed244e94b (diff)
downloadcoreboot-8907e816265d9821e39bb21333f6212b97e80504.tar.xz
move console includes to central console/console.h
Because it's included everywhere anyways. Change-Id: I99a9e6edac08df57c50ef3a706fdbd395cad0abc Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/691 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/include')
-rw-r--r--src/include/console/console.h17
-rw-r--r--src/include/uart8250.h31
2 files changed, 20 insertions, 28 deletions
diff --git a/src/include/console/console.h b/src/include/console/console.h
index 8283f66e90..54c825cdac 100644
--- a/src/include/console/console.h
+++ b/src/include/console/console.h
@@ -24,15 +24,21 @@
#include <console/loglevel.h>
#include <console/post_codes.h>
+#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM
+#include <uart8250.h>
+#endif
+#if CONFIG_USBDEBUG
+#include <usbdebug.h>
+#endif
+#if CONFIG_CONSOLE_NE2K
+#include <console/ne2k.h>
+#endif
+
#ifndef __PRE_RAM__
void console_tx_byte(unsigned char byte);
void console_tx_flush(void);
unsigned char console_rx_byte(void);
int console_tst_byte(void);
-#if CONFIG_USBDEBUG
-#include <usbdebug.h>
-#endif
-
struct console_driver {
void (*init)(void);
void (*tx_byte)(unsigned char byte);
@@ -55,9 +61,6 @@ extern int console_loglevel;
* we could use the same code on all architectures.
*/
#define console_loglevel CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-#if CONFIG_CONSOLE_SERIAL8250
-#include <uart8250.h>
-#endif
#endif
#ifndef __ROMCC__
diff --git a/src/include/uart8250.h b/src/include/uart8250.h
index 3c8ea09291..aa510e56f8 100644
--- a/src/include/uart8250.h
+++ b/src/include/uart8250.h
@@ -20,26 +20,7 @@
#ifndef UART8250_H
#define UART8250_H
-/* Base Address */
-#ifndef CONFIG_TTYS0_BASE
-#define CONFIG_TTYS0_BASE 0x3f8
-#endif
-
-#ifndef CONFIG_TTYS0_BAUD
-#define CONFIG_TTYS0_BAUD 115200
-#endif
-#if ((115200%CONFIG_TTYS0_BAUD) != 0)
-#error Bad ttys0 baud rate
-#endif
-
-/* Line Control Settings */
-#ifndef CONFIG_TTYS0_LCS
-/* Set 8bit, 1 stop bit, no parity */
-#define CONFIG_TTYS0_LCS 0x3
-#endif
-
-#define UART_LCS CONFIG_TTYS0_LCS
-
+#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM
/* Data */
#define UART_RBR 0x00
@@ -126,6 +107,12 @@
#define UART_SCR 0x07
#define UART_SPR 0x07
+#if ((115200 % CONFIG_TTYS0_BAUD) != 0)
+#error Bad ttyS0 baud rate
+#endif
+
+/* Line Control Settings */
+#define UART_LCS CONFIG_TTYS0_LCS
#ifndef __ROMCC__
unsigned char uart8250_rx_byte(unsigned base_port);
@@ -151,6 +138,8 @@ u32 uartmem_getbaseaddr(void);
/* and special init for OXPCIe based cards */
void oxford_init(void);
-#endif
+#endif /* __ROMCC__ */
+
+#endif /* CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM */
#endif /* UART8250_H */