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| author | Subrata Banik <subrata.banik@intel.com> | 2021-05-04 23:36:36 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-05-06 14:39:06 +0000 |
| commit | a2cf34129fb3b2a9302bb7cf06e4ee758b9bb85a (patch) | |
| tree | a80ebde191b4bb5ab279756a52b67b46ab308b4d /src/include | |
| parent | 88a0ce6e11601678ec8d8f6a87c4881b810cb5df (diff) | |
| download | coreboot-a2cf34129fb3b2a9302bb7cf06e4ee758b9bb85a.tar.xz | |
include/console: Align ramstage Boot State Machine postcodes
This patch ensures all boot state machine postcodes are in right
order. Move POST_ENTRY_RAMSTAGE macro definition after
POST_BS_PAYLOAD_BOOT.
Change-Id: I9e03159fdf07a73f5f8eec1bbf32fcb47dd4af84
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52893
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/console/post_codes.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index ee74dcb23e..677cd36545 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -182,14 +182,6 @@ #define POST_PRE_HARDWAREMAIN 0x79 /** - * \brief Entry into coreboot in RAM stage main() - * - * This is the first call in hardwaremain.c. If this code is POSTed, then - * ramstage has successfully loaded and started executing. - */ -#define POST_ENTRY_RAMSTAGE 0x80 - -/** * \brief Load Payload * * Boot State Machine: bs_payload_load() @@ -204,6 +196,14 @@ #define POST_BS_PAYLOAD_BOOT 0x7b /** + * \brief Entry into coreboot in RAM stage main() + * + * This is the first call in hardwaremain.c. If this code is POSTed, then + * ramstage has successfully loaded and started executing. + */ +#define POST_ENTRY_RAMSTAGE 0x80 + +/** * \brief Before calling FSP Notify before End of Firmware * * Going to call into FSP binary for Notify phase |