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authorNaresh G Solanki <naresh.solanki@intel.com>2016-10-26 19:43:14 +0530
committerAaron Durbin <adurbin@chromium.org>2016-11-30 17:02:19 +0100
commit335781ad53cd4988425e922cc24c966958484f0f (patch)
tree14cd51d39a8de9c271cef7ea461d515ea5b351e2 /src/include
parent500ba45b2c18a2742188d603808e2812fe6ed437 (diff)
downloadcoreboot-335781ad53cd4988425e922cc24c966958484f0f.tar.xz
lib: Add library to handle SPD data in CBFS or DIMM
Add library to: 1. add spd.bin in cbfs, generated from mainboard/spd/*.spd.hex files. 2. runtime get spd data with spd index as input. 3. fetch spd over smbus using early smbus functions. Change-Id: I44fe1cdb883dd1037484d4bb5c87d2d4f9862bf8 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17434 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/include')
-rw-r--r--src/include/spd_bin.h57
1 files changed, 57 insertions, 0 deletions
diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h
new file mode 100644
index 0000000000..a0c1bbda4f
--- /dev/null
+++ b/src/include/spd_bin.h
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SPD_BIN_H
+#define SPD_BIN_H
+
+#include <arch/early_variables.h>
+#include <stdint.h>
+#include <commonlib/region.h>
+
+#define SPD_PAGE_LEN 256
+#define SPD_PAGE_LEN_DDR4 512
+#define SPD_PAGE_0 (0x6C >> 1)
+#define SPD_PAGE_1 (0x6E >> 1)
+#define SPD_DRAM_TYPE 2
+#define SPD_DRAM_DDR3 0x0B
+#define SPD_DRAM_LPDDR3_INTEL 0xF1
+#define SPD_DRAM_LPDDR3_JEDEC 0x0F
+#define SPD_DRAM_DDR4 0x0C
+#define SPD_DENSITY_BANKS 4
+#define SPD_ADDRESSING 5
+#define SPD_ORGANIZATION 7
+#define SPD_BUS_DEV_WIDTH 8
+#define DDR3_SPD_PART_OFF 128
+#define DDR3_SPD_PART_LEN 18
+#define LPDDR3_SPD_PART_OFF 128
+#define LPDDR3_SPD_PART_LEN 18
+#define DDR4_SPD_PART_OFF 329
+#define DDR4_SPD_PART_LEN 20
+#define LPDDR4_SPD_PART_OFF 329
+#define LPDDR4_SPD_PART_LEN 20
+
+struct spd_block {
+ u8 *spd_array[CONFIG_DIMM_MAX];
+ /* Length of each dimm */
+ u16 len;
+};
+
+void print_spd_info(uint8_t spd[]);
+/* Return 0 on success & -1 on failure */
+int get_spd_cbfs_rdev(struct region_device *spd_rdev, u8 spd_index);
+void dump_spd_info(struct spd_block *blk);
+void get_spd_smbus(struct spd_block *blk);
+
+#endif