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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-06-19 20:38:41 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-06-22 11:03:42 +0200
commit65cc526f6f47755b4492cd9fc2134fb2dd067e90 (patch)
tree9b7357287b96f73a762592ccc8b7d2153eff1d46 /src/include
parentc5400efc11e181caf0babaa6001de18e3f23c6af (diff)
downloadcoreboot-65cc526f6f47755b4492cd9fc2134fb2dd067e90.tar.xz
Ignore RAMTOP for MTRRs
Without RELOCATABLE_RAMSTAGE have WB cache large enough to cover the greatest ramstage needs, as there is no benefit of trying to accurately match the actual need. Choose this to be bottom 16MiB. With RELOCATABLE_RAMSTAGE write-back cache of low ram is only useful for bottom 1MiB of RAM as a small part of this gets used during SMP initialisation before proper MTRR setup. Change-Id: Icd5f8461f81ed0e671130f1142641a48d1304f30 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15249 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/include')
-rw-r--r--src/include/cpu/x86/mtrr.h12
1 files changed, 5 insertions, 7 deletions
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 4eb4f135c3..f33a4ace4c 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -91,9 +91,11 @@ int get_free_var_mtrr(void);
(x>>6)|(x>>7)|(x>>8)|((1<<18)-1))
#define _ALIGN_UP_POW2(x) ((x + _POW2_MASK(x)) & ~_POW2_MASK(x))
-#if !defined(CONFIG_RAMTOP) || !CONFIG_RAMTOP
-# error "CONFIG_RAMTOP not configured"
-#endif
+/* At the end of romstage, low ram 0..CACHE_TM_RAMTOP may be set
+ * as write-back cacheable to speed up ramstage decompression.
+ * Note MTRR boundaries, must be power of two.
+ */
+#define CACHE_TMP_RAMTOP (16<<20)
#if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0)
# error "CONFIG_XIP_ROM_SIZE is not a power of 2"
@@ -122,8 +124,4 @@ int get_free_var_mtrr(void);
#define CACHE_ROM_BASE (((1<<20) - (CACHE_ROM_SIZE>>12))<<12)
-#if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0
-# error "CONFIG_RAMTOP must be a power of 2"
-#endif
-
#endif /* CPU_X86_MTRR_H */