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| author | Patrick Rudolph <siro@das-labor.org> | 2018-12-27 11:41:35 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-02-05 13:24:30 +0000 |
| commit | 6bbc8d8050b1d51ec4bf15003a2da54e20d476c7 (patch) | |
| tree | 8eab4601bfe8d880c1d4ecde36ca77c5273ea5b6 /src/include | |
| parent | 8d010db58e5cd9d26ff7c5c7d4dd93a6df0fcbb7 (diff) | |
| download | coreboot-6bbc8d8050b1d51ec4bf15003a2da54e20d476c7.tar.xz | |
cpu/x86/mtrr: Fix sign overflow
Use unsigned long to prevent sign overflow.
Fixes wrong MTRRs settings on x86_64 romstage.
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Change-Id: I71b61a45becc17bf60a619e4131864c82a16b0d1
Reviewed-on: https://review.coreboot.org/c/30502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/cpu/x86/mtrr.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index eb7d78d1c5..0398a2e1b0 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -150,7 +150,7 @@ static inline unsigned int fls(unsigned int x) #define _ALIGN_DOWN_POW2(x) ((x) & ~_POW2_MASK(x)) /* Calculate `4GiB - x` (e.g. absolute address for offset from 4GiB) */ -#define _FROM_4G_TOP(x) (((1 << 20) - ((x) >> 12)) << 12) +#define _FROM_4G_TOP(x) (((1UL << 20) - ((x) >> 12)) << 12) /* At the end of romstage, low RAM 0..CACHE_TM_RAMTOP may be set * as write-back cacheable to speed up ramstage decompression. |