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authorDuncan Laurie <dlaurie@chromium.org>2011-10-25 14:15:11 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-03-29 22:16:07 +0200
commit90dcdd43ee83b12ddd1cdafba7613971cbfa2117 (patch)
treea86c9e122215b93566e9f9174e8919f81b08a813 /src/include
parent22c0468d3927a370b9723e9e78714c2731d33a81 (diff)
downloadcoreboot-90dcdd43ee83b12ddd1cdafba7613971cbfa2117.tar.xz
Add support for enabling PCIe Common Clock and ASPM
These are guarded by individual Kconfig entries. The deprecated CONFIG_PCIE_TUNING defines have been removed in favor of using specific config options. This is the generic half, there is board-specific pieces still to come that tune before and after ASPM is enabled. Change-Id: I3fe46282eada67629e9eeeed07e487dff54f2729 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/735 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/include')
-rw-r--r--src/include/device/pci_def.h7
-rw-r--r--src/include/device/pciexp.h7
2 files changed, 14 insertions, 0 deletions
diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h
index a5aa3a1c3b..58a73218fe 100644
--- a/src/include/device/pci_def.h
+++ b/src/include/device/pci_def.h
@@ -371,8 +371,15 @@
#define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
#define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
+#define PCI_EXP_LNKCAP_ASPMS 0xc00 /* ASPM Support */
+#define PCI_EXP_LNKCAP_L0SEL 0x7000 /* L0s Exit Latency */
+#define PCI_EXP_LNKCAP_L1EL 0x38000 /* L1 Exit Latency */
#define PCI_EXP_LNKCTL 16 /* Link Control */
+#define PCI_EXP_LNKCTL_RL 0x20 /* Retrain Link */
+#define PCI_EXP_LNKCTL_CCC 0x40 /* Common Clock COnfiguration */
#define PCI_EXP_LNKSTA 18 /* Link Status */
+#define PCI_EXP_LNKSTA_LT 0x800 /* Link Training */
+#define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */
#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
#define PCI_EXP_SLTCTL 24 /* Slot Control */
#define PCI_EXP_SLTSTA 26 /* Slot Status */
diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h
index 409f211a82..87a5002c5e 100644
--- a/src/include/device/pciexp.h
+++ b/src/include/device/pciexp.h
@@ -2,6 +2,13 @@
#define DEVICE_PCIEXP_H
/* (c) 2005 Linux Networx GPL see COPYING for details */
+enum aspm_type {
+ PCIE_ASPM_NONE = 0,
+ PCIE_ASPM_L0S = 1,
+ PCIE_ASPM_L1 = 2,
+ PCIE_ASPM_BOTH = 3,
+};
+
unsigned int pciexp_scan_bus(struct bus *bus, unsigned int min_devfn,
unsigned int max_devfn, unsigned int max);
unsigned int pciexp_scan_bridge(device_t dev, unsigned int max);