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authorDuncan Laurie <dlaurie@chromium.org>2012-09-09 19:09:56 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-11-08 19:40:40 +0100
commitb6e97b19ae6a68556838c9801c7824302d72151f (patch)
tree0afd66b23e15ca3429134cf061f3ba9e12efc7cd /src/include
parent31409617a46c5ac6ef1a893d3c478f76ce4d7d3d (diff)
downloadcoreboot-b6e97b19ae6a68556838c9801c7824302d72151f.tar.xz
Add support for storing POST codes in CMOS
This will use 3 bytes of CMOS to keep track of the POST code for the current boot while also leaving a record of the previous boot. The active bank is switched early in the bootblock. Test: 1) clear cmos 2) reboot 3) use "mosys nvram dump" to verify that the first byte contains 0x80 and the second byte contains 0xF8 4) powerd_suspend and then resume 5) use "mosys nvram dump" to verify that the first byte contains 0x81 and the second byte contains 0xFD Change-Id: I1ee6bb2dac053018f3042ab5a0b26c435dbfd151 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1743 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/include')
-rw-r--r--src/include/pc80/mc146818rtc.h19
1 files changed, 19 insertions, 0 deletions
diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h
index 61b522ca74..edc3241e42 100644
--- a/src/include/pc80/mc146818rtc.h
+++ b/src/include/pc80/mc146818rtc.h
@@ -158,4 +158,23 @@ static inline int get_option(void *dest __attribute__((unused)),
#endif
#define read_option(name, default) read_option_lowlevel(CMOS_VSTART_ ##name, CMOS_VLEN_ ##name, (default))
+#if CONFIG_CMOS_POST
+#if CONFIG_USE_OPTION_TABLE
+# include "option_table.h"
+# define CMOS_POST_OFFSET (CMOS_VSTART_cmos_post_offset >> 3)
+#else
+# if defined(CONFIG_CMOS_POST_OFFSET)
+# define CMOS_POST_OFFSET CONFIG_CMOS_POST_OFFSET
+# else
+# error "Must define CONFIG_CMOS_POST_OFFSET"
+# endif
+#endif
+
+#define CMOS_POST_BANK_OFFSET (CMOS_POST_OFFSET)
+#define CMOS_POST_BANK_0_MAGIC 0x80
+#define CMOS_POST_BANK_0_OFFSET (CMOS_POST_OFFSET + 1)
+#define CMOS_POST_BANK_1_MAGIC 0x81
+#define CMOS_POST_BANK_1_OFFSET (CMOS_POST_OFFSET + 2)
+#endif /* CONFIG_CMOS_POST */
+
#endif /* PC80_MC146818RTC_H */