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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2017-11-23 21:23:44 +0100 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2017-11-30 17:21:17 +0000 |
| commit | 242ea84b017b7f2812a4a1ba4b4996e5f1bb35ab (patch) | |
| tree | bd104e859220d84d30f56c3acb689ff7e0ca17b9 /src/include | |
| parent | 3df9dbe8864adf6d41df2fe617c8818d1bad9d42 (diff) | |
| download | coreboot-242ea84b017b7f2812a4a1ba4b4996e5f1bb35ab.tar.xz | |
intel: Replace msr(0x198) with msr(IA32_PERF_STATUS)
Change-Id: I22241427d1405de2e2eb2b3cfb029f3ce2c8dace
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/22585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/cpu/intel/speedstep.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index 40234d5fca..59336ed0c6 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -36,7 +36,7 @@ /* Speedstep related MSRs */ #define IA32_PLATFORM_ID 0x017 -#define IA32_PERF_STS 0x198 +#define IA32_PERF_STATUS 0x198 #define IA32_PERF_CTL 0x199 #define MSR_THERM2_CTL 0x19D #define IA32_MISC_ENABLES 0x1A0 |