diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-11-01 02:13:17 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-11-03 21:55:20 +0100 |
| commit | 3bfd7cc61e73439a2b1ac2d85faa7aaa988969ed (patch) | |
| tree | 2efc202d627313811141f9d42bf24d80cccd41a8 /src/include | |
| parent | 2a4f58ac1283e45d1f0cc6102a319b6d442a888d (diff) | |
| download | coreboot-3bfd7cc61e73439a2b1ac2d85faa7aaa988969ed.tar.xz | |
drivers/pc80: Rework normal / fallback selector code
Per IRC and Gerrit discussion, the normal / fallback
selector code is a rather weak spot in coreboot, and
did not function correctly for certain use cases.
Rework the selector to more clearly indicate proper
operation, and also remove dead code. Also tentatively
abandon use of RTC bit 385; a follow-up patch will
remove said bit from all affected mainboards.
The correct operation of the fallback code selector
approximates that of a power line recloser, with
a user option to attempt normal boot that can be
cleared by firmware, but never set by firmware.
Additionally, if cleared by user, the fallback
path should always be used on the next reboot.
Change-Id: I753ae9f0710c524875a85354ac2547df0c305569
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12289
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/pc80/mc146818rtc.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 0e15273fc4..38f2ad085c 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -25,6 +25,8 @@ **********************************************************************/ #define RTC_FREQ_SELECT RTC_REG_A +#define RTC_BOOT_NORMAL 0x1 + /* update-in-progress - set to "1" 244 microsecs before RTC goes off the bus, * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete, * totaling to a max high interval of 2.228 ms. |