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authorStefan Reinauer <stepan@openbios.org>2005-12-02 21:52:30 +0000
committerStefan Reinauer <stepan@openbios.org>2005-12-02 21:52:30 +0000
commit7ce8c54e2ba89059d28790550a8f74907b54b916 (patch)
treee89df947fbe9e3f85d6082af6926038e9fe8e61a /src/include
parentc2455dc0ce210b3da2b14be8885803ff47a781eb (diff)
downloadcoreboot-7ce8c54e2ba89059d28790550a8f74907b54b916.tar.xz
1201_ht_bus0_dev0_fidvid_core.diff
https://openbios.org/roundup/linuxbios/issue41 Lord have mercy upon us. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2118 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/include')
-rw-r--r--src/include/cpu/amd/dualcore.h16
-rw-r--r--src/include/cpu/x86/lapic.h11
-rw-r--r--src/include/device/hypertransport.h2
-rw-r--r--src/include/device/pci_ids.h55
4 files changed, 62 insertions, 22 deletions
diff --git a/src/include/cpu/amd/dualcore.h b/src/include/cpu/amd/dualcore.h
index a38565b01f..fb53c92909 100644
--- a/src/include/cpu/amd/dualcore.h
+++ b/src/include/cpu/amd/dualcore.h
@@ -1,14 +1,24 @@
#ifndef CPU_AMD_DUALCORE_H
#define CPU_AMD_DUALCORE_H
-struct device;
+#if defined(__GNUC__)
+unsigned int read_nb_cfg_54(void);
+#endif
struct node_core_id {
unsigned nodeid;
unsigned coreid;
};
-void amd_sibling_init(struct device *cpu, struct node_core_id id);
-struct node_core_id get_node_core_id(void);
+#if defined(__GNUC__)
+// it can be used to get unitid and coreid it running only
+struct node_core_id get_node_core_id(unsigned int nb_cfg_54);
+#endif
+
+#ifndef __ROMCC__
+struct device;
+unsigned get_apicid_base(unsigned ioapic_num);
+void amd_sibling_init(struct device *cpu);
+#endif
#endif /* CPU_AMD_DUALCORE_H */
diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h
index 12ca518f66..5d696dce18 100644
--- a/src/include/cpu/x86/lapic.h
+++ b/src/include/cpu/x86/lapic.h
@@ -10,17 +10,17 @@
# define NEED_LAPIC 1
#endif
-static inline unsigned long lapic_read(unsigned long reg)
+static inline __attribute__((always_inline)) unsigned long lapic_read(unsigned long reg)
{
return *((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg));
}
-static inline void lapic_write(unsigned long reg, unsigned long v)
+static inline __attribute__((always_inline)) void lapic_write(unsigned long reg, unsigned long v)
{
*((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg)) = v;
}
-static inline void lapic_wait_icr_idle(void)
+static inline __attribute__((always_inline)) void lapic_wait_icr_idle(void)
{
do { } while ( lapic_read( LAPIC_ICR ) & LAPIC_ICR_BUSY );
}
@@ -46,13 +46,14 @@ static inline void disable_lapic(void)
wrmsr(LAPIC_BASE_MSR, msr);
}
-static inline unsigned long lapicid(void)
+static inline __attribute__((always_inline)) unsigned long lapicid(void)
{
return lapic_read(LAPIC_ID) >> 24;
}
-static inline void stop_this_cpu(void)
+static inline __attribute__((always_inline)) void stop_this_cpu(void)
{
+
unsigned apicid;
apicid = lapicid();
diff --git a/src/include/device/hypertransport.h b/src/include/device/hypertransport.h
index f04d0eca30..8eba981745 100644
--- a/src/include/device/hypertransport.h
+++ b/src/include/device/hypertransport.h
@@ -4,7 +4,7 @@
#include <device/hypertransport_def.h>
unsigned int hypertransport_scan_chain(struct bus *bus,
- unsigned min_devfn, unsigned max_devfn, unsigned int max);
+ unsigned min_devfn, unsigned max_devfn, unsigned int max, unsigned offset_unitid);
unsigned int ht_scan_bridge(struct device *dev, unsigned int max);
extern struct device_operations default_ht_ops_bus;
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 373b73c2ee..d219b96fe1 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -438,6 +438,9 @@
#define PCI_DEVICE_ID_AMD_8131_PCIX 0x7450
#define PCI_DEVICE_ID_AMD_8131_IOAPIC 0x7451
+#define PCI_DEVICE_ID_AMD_8132_PCIX 0x7458
+#define PCI_DEVICE_ID_AMD_8132_IOAPIC 0x7459
+
#define PCI_VENDOR_ID_TRIDENT 0x1023
#define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX 0x2000
#define PCI_DEVICE_ID_TRIDENT_4DWAVE_NX 0x2001
@@ -910,6 +913,20 @@
#define PCI_DEVICE_ID_CERN_HIPPI_DST 0x0021
#define PCI_DEVICE_ID_CERN_HIPPI_SRC 0x0022
+#define PCI_DEVICE_ID_NVIDIA_CK8S_HT 0x00e1
+#define PCI_DEVICE_ID_NVIDIA_CK8S_LPC 0x00e0
+#define PCI_DEVICE_ID_NVIDIA_CK8S_SM 0x00e4
+#define PCI_DEVICE_ID_NVIDIA_CK8S_USB 0x00e7
+#define PCI_DEVICE_ID_NVIDIA_CK8S_USB2 0x00e8
+#define PCI_DEVICE_ID_NVIDIA_CK8S_NIC 0x00e6
+#define PCI_DEVICE_ID_NVIDIA_CK8S_ACI 0x00ea
+#define PCI_DEVICE_ID_NVIDIA_CK8S_MCI 0x00e9
+#define PCI_DEVICE_ID_NVIDIA_CK8S_IDE 0x00e5
+#define PCI_DEVICE_ID_NVIDIA_CK8S_SATA0 0x00ee
+#define PCI_DEVICE_ID_NVIDIA_CK8S_SATA1 0x00e3
+#define PCI_DEVICE_ID_NVIDIA_CK8S_PCI 0x00ed
+#define PCI_DEVICE_ID_NVIDIA_CK8S_PCI_AGP 0x00e2
+
#define PCI_VENDOR_ID_NVIDIA 0x10de
#define PCI_DEVICE_ID_NVIDIA_TNT 0x0020
#define PCI_DEVICE_ID_NVIDIA_TNT2 0x0028
@@ -1060,8 +1077,8 @@
#define PCI_DEVICE_ID_VIA_8233C_0 0x3109
#define PCI_DEVICE_ID_VIA_8361 0x3112
#define PCI_DEVICE_ID_VIA_8233A 0x3147
-#define PCI_DEVICE_ID_VIA_CLE266_VGA 0x3122
-#define PCI_DEVICE_ID_VIA_8623 0x3123
+#define PCI_DEVICE_ID_VIA_CLE266_VGA 0x3122
+#define PCI_DEVICE_ID_VIA_8623 0x3123
#define PCI_DEVICE_ID_VIA_86C100A 0x6100
#define PCI_DEVICE_ID_VIA_8231 0x8231
#define PCI_DEVICE_ID_VIA_8231_4 0x8235
@@ -1207,6 +1224,21 @@
#define PCI_DEVICE_ID_SERVERWORKS_GCLE2 0x0227
#define PCI_DEVICE_ID_SERVERWORKS_CSB5ISA 0x0230
+#define PCI_DEVICE_ID_SERVERWORKS_BCM5780_PXB 0x0130
+#define PCI_DEVICE_ID_SERVERWORKS_BCM5780_PCIE 0x0132
+#define PCI_DEVICE_ID_BROADCOM_BCM5780_NIC 0x1668
+#define PCI_DEVICE_ID_BROADCOM_BCM5780_NIC1 0x1669
+
+#define PCI_DEVICE_ID_SERVERWORKS_BCM5785_HT_PXB 0x0036
+#define PCI_DEVICE_ID_SERVERWORKS_BCM5785_PXBX 0x0104
+#define PCI_DEVICE_ID_SERVERWORKS_BCM5785_SATA 0x024a
+#define PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN 0x0205
+#define PCI_DEVICE_ID_SERVERWORKS_BCM5785_IDE 0x0214
+#define PCI_DEVICE_ID_SERVERWORKS_BCM5785_LPC 0x0234
+#define PCI_DEVICE_ID_SERVERWORKS_BCM5785_WDT 0x0238
+#define PCI_DEVICE_ID_SERVERWORKS_BCM5785_XIOAPIC 0x0235
+#define PCI_DEVICE_ID_SERVERWORKS_BCM5785_USB 0x0223
+
#define PCI_VENDOR_ID_SBE 0x1176
#define PCI_DEVICE_ID_SBE_WANXL100 0x0301
#define PCI_DEVICE_ID_SBE_WANXL200 0x0302
@@ -1763,7 +1795,6 @@
#define PCI_DEVICE_ID_INTEL_82801CA_1F3 0x2483
#define PCI_DEVICE_ID_INTEL_82801CA_1D1 0x2484
#define PCI_DEVICE_ID_INTEL_82801CA_1F5 0x2485
-#define PCI_DEVICE_ID_INTEL_82801CA_1F6 0x2486
#define PCI_DEVICE_ID_INTEL_82801CA_1D2 0x2487
#define PCI_DEVICE_ID_INTEL_82870_1E0 0x1461
#define PCI_DEVICE_ID_INTEL_82870_1F0 0x1460
@@ -1793,17 +1824,15 @@
#define PCI_DEVICE_ID_INTEL_82801E_11 0x245b
#define PCI_DEVICE_ID_INTEL_82801E_13 0x245d
#define PCI_DEVICE_ID_INTEL_82801E_14 0x245e
-#define PCI_DEVICE_ID_INTEL_82801CA_LAN 0x2449
-#define PCI_DEVICE_ID_INTEL_82801CA_PCI 0x244e // Same as 82801ER
-#define PCI_DEVICE_ID_INTEL_82801CA_LPC 0x2480
-#define PCI_DEVICE_ID_INTEL_82801CA_USB 0x2482
-#define PCI_DEVICE_ID_INTEL_82801CA_SMB 0x2483
-#define PCI_DEVICE_ID_INTEL_82801CA_USB2 0x2484
-#define PCI_DEVICE_ID_INTEL_82801CA_AC97_AUDIO 0x2485
-#define PCI_DEVICE_ID_INTEL_82801CA_AC97_MODEM 0x2486
-#define PCI_DEVICE_ID_INTEL_82801CA_USB3 0x2487
+#define PCI_DEVICE_ID_INTEL_82801CA_0 0x2480
+#define PCI_DEVICE_ID_INTEL_82801CA_2 0x2482
+#define PCI_DEVICE_ID_INTEL_82801CA_3 0x2483
+#define PCI_DEVICE_ID_INTEL_82801CA_4 0x2484
+#define PCI_DEVICE_ID_INTEL_82801CA_5 0x2485
+#define PCI_DEVICE_ID_INTEL_82801CA_6 0x2486
+#define PCI_DEVICE_ID_INTEL_82801CA_7 0x2487
#define PCI_DEVICE_ID_INTEL_82801CA_10 0x248a
-#define PCI_DEVICE_ID_INTEL_82801CA_IDE 0x248b
+#define PCI_DEVICE_ID_INTEL_82801CA_11 0x248b
#define PCI_DEVICE_ID_INTEL_82801CA_12 0x248c
#define PCI_DEVICE_ID_INTEL_82801DB_0 0x24c0
#define PCI_DEVICE_ID_INTEL_82801DB_2 0x24c2