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| author | Ronald G. Minnich <rminnich@gmail.com> | 2018-09-16 09:59:54 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-11 17:42:41 +0000 |
| commit | 83bd46e5e5df0176af1208c7feec98d64273875b (patch) | |
| tree | a9b8905d9bb14b127a0b1d996ff5a712d721cab0 /src/include | |
| parent | ce1064edd6827112ee86728ac15f67daab656f54 (diff) | |
| download | coreboot-83bd46e5e5df0176af1208c7feec98d64273875b.tar.xz | |
selfboot: remove bounce buffers
Bounce buffers used to be used in those cases where the payload
might overlap coreboot.
Bounce buffers are a problem for rampayloads as they need malloc.
They are also an artifact of our x86 past before we had relocatable
ramstage; only x86, out of the 5 architectures we support, needs them;
currently they only seem to matter on the following chipsets:
src/northbridge/amd/amdfam10/Kconfig
src/northbridge/amd/lx/Kconfig
src/northbridge/via/vx900/Kconfig
src/soc/intel/fsp_baytrail/Kconfig
src/soc/intel/fsp_broadwell_de/Kconfig
The first three are obsolete or at least could be changed
to avoid the need to have bounce buffers.
The last two should change to no longer need them.
In any event they can be fixed or pegged to a release which supports
them.
For these five chipsets we change CONFIG_RAMBASE from 0x100000 (the
value needed in 1999 for the 32-bit Linux kernel, the original ramstage)
to 0xe00000 (14 Mib) which will put the non-relocatable x86
ramstage out of the way of any reasonable payload until we can
get rid of it for good.
14 MiB was chosen after some discussion, but it does fit well:
o Fits in the 16 MiB cacheable range coreboot sets up by default
o Most small payloads are well under 14 MiB (even kernels!)
o Most large payloads get loaded at 16 MiB (especially kernels!)
With this change in place coreboot correctly still loads a bzImage payload.
Werner reports that the 0xe00000 setting works on his broadwell systems.
Change-Id: I602feb32f35e8af1d0dc4ea9f25464872c9b824c
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/28647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/bootmem.h | 5 | ||||
| -rw-r--r-- | src/include/program_loading.h | 3 |
2 files changed, 0 insertions, 8 deletions
diff --git a/src/include/bootmem.h b/src/include/bootmem.h index 28bc95bae8..0a960c992a 100644 --- a/src/include/bootmem.h +++ b/src/include/bootmem.h @@ -97,11 +97,6 @@ bool bootmem_walk(range_action_t action, void *arg); /* Return 1 if region targets usable RAM, 0 otherwise. */ int bootmem_region_targets_usable_ram(uint64_t start, uint64_t size); -/* Return 1 if region targets usable RAM, and we allow memory ranges - * with type >BM_MEM_OS_CUTOFF to be overwritten at the time we jump - * to payload. 0 otherwise. */ -int bootmem_region_usable_with_bounce(uint64_t start, uint64_t size); - /* Allocate a temporary buffer from the unused RAM areas. */ void *bootmem_allocate_buffer(size_t size); diff --git a/src/include/program_loading.h b/src/include/program_loading.h index 482c8b8995..aa21cf57ab 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -49,9 +49,6 @@ void prog_segment_loaded(uintptr_t start, size_t size, int flags); void platform_segment_loaded(uintptr_t start, size_t size, int flags); void arch_segment_loaded(uintptr_t start, size_t size, int flags); -/* Return true if arch supports bounce buffer. */ -int arch_supports_bounce_buffer(void); - /* Representation of a program. */ struct prog { /* The region_device is the source of program content to load. After |