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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-02-10 22:21:39 -0600 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-02-16 21:02:30 +0100 |
| commit | 033bb4bc8d620288ed82fe982a32f567060499b6 (patch) | |
| tree | bba24a07d463455825363b54894da14a6ba07025 /src/include | |
| parent | 4f731f2eabc9ef2c381b71515a3b2ff203c8653e (diff) | |
| download | coreboot-033bb4bc8d620288ed82fe982a32f567060499b6.tar.xz | |
acpi: Generate valid ACPI processor objects
The existing code generated invalid ACPI processor objects
if the core number was greater than 9. The first invalid
object instance was autocorrected by Linux, but subsequent
instances conflicted with each other, leading to a failure
to boot if more than 10 CPU cores were installed.
The modified code will function with up to 99 cores.
Change-Id: I62dc0eb61ae2e2b7f7dcf30e9c7de09cd901a81c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8422
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/cpu/intel/speedstep.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index 8bfae60c1f..eb8b50607c 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -29,7 +29,7 @@ #define SPEEDSTEP_APIC_MAGIC 0xACAC /* MWAIT coordination I/O base address. This must match - * the \_PR_.CPU0 PM base address. + * the \_PR_.CP00 PM base address. */ #define PMB0_BASE 0x510 |