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authorMarshall Dawson <marshalldawson3rd@gmail.com>2017-12-13 12:04:14 -0700
committerMartin Roth <martinroth@google.com>2017-12-20 16:36:43 +0000
commit1731a33e322e3760de2ffb5349923a592ebe97ac (patch)
tree0d99d79c99e2632769f5f3e1f9630651ec012b39 /src/include
parentd1cc3c213f94c6a75cf4613bf302c7a8f8c06b14 (diff)
downloadcoreboot-1731a33e322e3760de2ffb5349923a592ebe97ac.tar.xz
include/cpu/x86: Add clflush inline function
Change-Id: I74c5cc22f02302314ba010bc599051c1495a13cb Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/include')
-rw-r--r--src/include/cpu/x86/cache.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h
index 2c8c44b531..e0a335971b 100644
--- a/src/include/cpu/x86/cache.h
+++ b/src/include/cpu/x86/cache.h
@@ -50,6 +50,11 @@ static inline void invd(void)
asm volatile("invd" ::: "memory");
}
+static inline void clflush(void *addr)
+{
+ asm volatile ("clflush (%0)"::"r" (addr));
+}
+
/* The following functions require the always_inline due to AMD
* function STOP_CAR_AND_CPU that disables cache as
* RAM, the cache as RAM stack can no longer be used. Called