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| author | Furquan Shaikh <furquan@google.com> | 2018-10-16 11:54:37 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-18 12:46:12 +0000 |
| commit | 585210ad587675067d59e8f408be4d2f5a860acf (patch) | |
| tree | 2775080efacaedf9752f157a11c2a63dcc29aa5a /src/include | |
| parent | 9706359fd8077e4027f6c8c8586bc40bdbb3a3f7 (diff) | |
| download | coreboot-585210ad587675067d59e8f408be4d2f5a860acf.tar.xz | |
drivers/intel/fsp*: Use newly added post codes for memory param prep
This change replaces use of post codes 0x34 and 0x36 in fsp drivers to
instead use POST_MEM_PREINIT_PREP_{START,END} to make it easy to
search from where these post codes are generated during boot flow.
Additionally, it adds POST_MEM_PREINIT_PREP_END to fsp2_0 memory_init
to make it consistent with fsp1_1 memory init.
Change-Id: I307ada1679f212c424e9f7ad2c9d254e24f41fd3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/include')
0 files changed, 0 insertions, 0 deletions