Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-51

Creator:  Yinghai Lu <yhlu@tyan.com>

cache_as_ram for AMD and some intel


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

6 files changed, 12 insertions, 10 deletions

diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h
index 572997bae3..2b7017d897 100644
--- a/src/include/cpu/amd/mtrr.h
+++ b/src/include/cpu/amd/mtrr.h
@@ -31,7 +31,7 @@
 #define TOP_MEM_MASK			0x007fffff
 #define TOP_MEM_MASK_KB			(TOP_MEM_MASK >> 10)
 
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined (ASSEMBLY)
 void amd_setup_mtrrs(void);
 #endif /* __ROMCC__ */
 
diff --git a/src/include/cpu/x86/bist.h b/src/include/cpu/x86/bist.h
index 6a62150c68..ff66eabe9b 100644
--- a/src/include/cpu/x86/bist.h
+++ b/src/include/cpu/x86/bist.h
@@ -4,9 +4,14 @@
 static void report_bist_failure(unsigned long bist)
 {
 	if (bist != 0) {
+#if CONFIG_USE_INIT
+                printk_emerg("BIST failed: %08x", bist);
+#else
 		print_emerg("BIST failed: ");
 		print_emerg_hex32(bist);
+#endif
 		die("\r\n");
+
 	}
 }
 
diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h
index 623ef971ce..af7d3d52ef 100644
--- a/src/include/cpu/x86/cache.h
+++ b/src/include/cpu/x86/cache.h
@@ -41,7 +41,7 @@ static inline void disable_cache(void)
 	wbinvd();
 }
 
-#ifndef __ROMCC__
+#if !defined( __ROMCC__)  && defined (__GNUC__)
 void x86_enable_cache(void);
 #endif /* !__ROMCC__ */
 
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index 4f481bdf4b..c4bc55a343 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -1,8 +1,7 @@
 #ifndef CPU_X86_MSR_H
 #define CPU_X86_MSR_H
 
-
-#ifdef __ROMCC__
+#if defined( __ROMCC__) && !defined (__GNUC__)
 
 typedef __builtin_msr_t msr_t;
 
@@ -16,9 +15,7 @@ static void wrmsr(unsigned long index, msr_t msr)
 	__builtin_wrmsr(index, msr.lo, msr.hi);
 }
 
-#endif /* __ROMCC__ */
-
-#if defined(__GNUC__) && !defined(__ROMCC__)
+#else
 
 typedef struct msr_struct 
 {
@@ -46,7 +43,7 @@ static inline void wrmsr(unsigned index, msr_t msr)
 		);
 }
 
-#endif /* __GNUC__ */
+#endif /* ROMCC__ && !__GNUC__ */
 
 
 #endif /* CPU_X86_MSR_H */
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index eb9bcb4169..3d229d23b9 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -32,7 +32,7 @@
 #define MTRRfix4K_F8000_MSR 0x26f
 
 
-#if !defined(__ROMCC__) && !defined(ASSEMBLY)
+#if !defined(__ROMCC__) && !defined (ASSEMBLY)
 
 void x86_setup_mtrrs(void);
 int x86_mtrr_check(void);
diff --git a/src/include/delay.h b/src/include/delay.h
index 0ffad4e611..bae75d34bf 100644
--- a/src/include/delay.h
+++ b/src/include/delay.h
@@ -1,6 +1,6 @@
 #ifndef DELAY_H
 #define DELAY_H
-#ifndef __ROMCC__
+#if !defined( __ROMCC__) && defined (__GNUC__)
 
 void udelay(unsigned usecs);
 void mdelay(unsigned msecs);