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authorSubrata Banik <subrata.banik@intel.com>2017-12-14 11:14:17 +0530
committerAaron Durbin <adurbin@chromium.org>2017-12-14 18:39:01 +0000
commit73ff712082607204025d229374557010d8686061 (patch)
treec031590ab660cfb9c84d1f5cc87a6303cf222e42 /src/include
parent96b2de93030c1f87ebfe05ecfb69682cf4d7f06a (diff)
downloadcoreboot-73ff712082607204025d229374557010d8686061.tar.xz
soc/intel/cannonlake: Fix UART2 serial log broken issue
Cannonlake rvp serial log has been regressed with commit I7eea910e065242689e87adac41281131674b39af(soc/intel/cannonlake: Clean up UART code) because of common UART code is unable to link all __weak function implementation from SoC uart.c due to existing macro #define __SIMPLE_DEVICE__. Hence UART2 PCI device resource programming is different than what it's been programmed before. This patch ensures UART2 PCI device resource enumeration is working and we are getting serial log as expected. Change-Id: I1f9df5e8d6490090ed65b06bdd0b40f824d36a8a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22862 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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