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| author | Wonkyu Kim <wonkyu.kim@intel.com> | 2020-01-07 23:40:58 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-01-22 15:42:12 +0000 |
| commit | 8406179eff18144cad3584f28554186baf8e1a37 (patch) | |
| tree | 8c327435703459c20452dc0255fc988a02ed49b9 /src/include | |
| parent | 13471bc86454ec33ca1550706d62386625e7fed1 (diff) | |
| download | coreboot-8406179eff18144cad3584f28554186baf8e1a37.tar.xz | |
soc/intel/tigerlake: Update interrupt info
Update interrupt header and interrupt mapping per Intel Silcon reference code.
Need to match pci_irqs.asl with FSP setting which followed by PCH BIOS spec.
Reference
PCH BIOS spec#613495
https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/master/ClientOneSiliconPkg
/IpBlock/Itss/LibraryPrivate/PeiItssPolicyLib/PeiItssPolicyLibVer2.c
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Iffc4efad4d0aa55fc0de88d7fe32c0356dbc3c60
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38258
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include')
0 files changed, 0 insertions, 0 deletions