diff options
| author | Dan Ehrenberg <dehrenberg@chromium.org> | 2015-01-08 10:29:19 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-17 09:21:07 +0200 |
| commit | a5aac76ac6be23448c164b0bc8047facb7238cdf (patch) | |
| tree | 50bdd770ce2e8b1d257cd6c9cf56fd5cd8635b52 /src/include | |
| parent | f9b49e8782efb7628984e1f3c3abc1ef7a58b84b (diff) | |
| download | coreboot-a5aac76ac6be23448c164b0bc8047facb7238cdf.tar.xz | |
drivers/spi: Pass flash parameters from coreboot to payload
A payload may want to run erase operations on SPI NOR flash without
re-probing the device to get its properties. This patch passes up
three properties of flash to achieve that:
- The size of the flash device
- The sector size, i.e., the granularity of erase
- The command used for erase
The patch sends the parameters through coreboot and then libpayload.
The patch also includes a minor refactoring of the flash erase code.
Parameters are sent up for just one flash device. If multiple SPI
flash devices are probed, the second one will "win" and its
parameters will be sent up to the payload.
TEST=Observed parameters to be passed up to depthcharge through
libpayload and be used to correctly initialize flash and do an erase.
TEST=Winbond and Gigadevices spi flash drivers compile with the changes;
others don't, for seemingly unrelated reasons.
BRANCH=none
BUG=chromium:446377
Change-Id: Ib8be86494b5a3d1cfe1d23d3492e3b5cba5f99c6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 988c8c68bbfcdfa69d497ea5f806567bc80f8126
Original-Change-Id: Ie2b3a7f5b6e016d212f4f9bac3fabd80daf2ce72
Original-Signed-off-by: Dan Ehrenberg <dehrenberg@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/239570
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9726
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/boot/coreboot_tables.h | 9 | ||||
| -rw-r--r-- | src/include/spi_flash.h | 5 |
2 files changed, 14 insertions, 0 deletions
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index a3cf2bd761..74851b2fbb 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -286,6 +286,15 @@ struct lb_ram_code { uint32_t ram_code; }; +#define LB_TAG_SPI_FLASH 0x0029 +struct lb_spi_flash { + uint32_t tag; + uint32_t size; + uint32_t flash_size; + uint32_t sector_size; + uint32_t erase_cmd; +}; + /* The following structures are for the cmos definitions table */ #define LB_TAG_CMOS_OPTION_TABLE 200 /* cmos header record */ diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index 8b8b0c54fe..cbb5919332 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -27,6 +27,7 @@ #include <stddef.h> #include <console/console.h> #include <spi-generic.h> +#include <boot/coreboot_tables.h> struct spi_flash { struct spi_slave *spi; @@ -37,6 +38,8 @@ struct spi_flash { u32 sector_size; + u8 erase_cmd; + int (*read)(struct spi_flash *flash, u32 offset, size_t len, void *buf); int (*write)(struct spi_flash *flash, u32 offset, @@ -47,4 +50,6 @@ struct spi_flash { struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs); +void lb_spi_flash(struct lb_header *header); + #endif /* _SPI_FLASH_H_ */ |