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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-07-24 08:03:37 -0700 |
|---|---|---|
| committer | Lee Leahy <leroy.p.leahy@intel.com> | 2016-07-27 13:50:11 +0200 |
| commit | ae738acdc5f02d232e035538c67d63ba19b9ccaa (patch) | |
| tree | 862a877545dad919c698b48381a115bd15130fcc /src/include | |
| parent | 7c2e5396a3d47c64eb5a553fe412aad4c0f8dc1b (diff) | |
| download | coreboot-ae738acdc5f02d232e035538c67d63ba19b9ccaa.tar.xz | |
cpu/x86: Support CPUs without rdmsr/wrmsr instructions
Quark does not support the rdmsr and wrmsr instructions. In this case
use a SOC specific routine to support the setting of the MTRRs. Migrate
the code from FSP 1.1 to be x86 CPU common.
Since all rdmsr/wrmsr accesses are being converted, fix the build
failure for quark in lib/reg_script.c. Move the soc_msr_x routines and
their depencies from romstage/mtrr.c to reg_access.c.
TEST=Build and run on Galileo Gen2
Change-Id: Ibc68e696d8066fbe2322f446d8c983d3f86052ea
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15839
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/cpu/x86/msr.h | 21 | ||||
| -rw-r--r-- | src/include/cpu/x86/mtrr.h | 13 |
2 files changed, 33 insertions, 1 deletions
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 40926df602..d644eddc2a 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -29,6 +29,23 @@ typedef struct msrinit_struct msr_t msr; } msrinit_t; +#if IS_ENABLED(CONFIG_SOC_SETS_MSRS) +msr_t soc_msr_read(unsigned index); +void soc_msr_write(unsigned index, msr_t msr); + +/* Handle MSR references in the other source code */ +static inline __attribute__((always_inline)) msr_t rdmsr(unsigned index) +{ + return soc_msr_read(index); +} + +static inline __attribute__((always_inline)) void wrmsr(unsigned index, + msr_t msr) +{ + soc_msr_write(index, msr); +} +#else /* CONFIG_SOC_SETS_MSRS */ + /* The following functions require the always_inline due to AMD * function STOP_CAR_AND_CPU that disables cache as * ram, the cache as ram stack can no longer be used. Called @@ -50,7 +67,8 @@ static inline __attribute__((always_inline)) msr_t rdmsr(unsigned index) return result; } -static inline __attribute__((always_inline)) void wrmsr(unsigned index, msr_t msr) +static inline __attribute__((always_inline)) void wrmsr(unsigned index, + msr_t msr) { __asm__ __volatile__ ( "wrmsr" @@ -59,6 +77,7 @@ static inline __attribute__((always_inline)) void wrmsr(unsigned index, msr_t ms ); } +#endif /* CONFIG_SOC_SETS_MSRS */ #endif /* __ROMCC__ */ #endif /* CPU_X86_MSR_H */ diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index f33a4ace4c..d09c77e2af 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -124,4 +124,17 @@ int get_free_var_mtrr(void); #define CACHE_ROM_BASE (((1<<20) - (CACHE_ROM_SIZE>>12))<<12) +#if (IS_ENABLED(CONFIG_SOC_SETS_MSRS) && !defined(__ASSEMBLER__) \ + && !defined(__ROMCC__)) +#include <cpu/x86/msr.h> +#include <arch/cpu.h> + +/* + * Set the MTRRs using the data on the stack from setup_stack_and_mtrrs. + * Return a new top_of_stack value which removes the setup_stack_and_mtrrs data. + */ +asmlinkage void *soc_set_mtrrs(void *top_of_stack); +asmlinkage void soc_enable_mtrrs(void); +#endif /* CONFIG_SOC_SETS_MSRS ... */ + #endif /* CPU_X86_MTRR_H */ |