summaryrefslogtreecommitdiff
path: root/src/include
diff options
context:
space:
mode:
authorAngel Pons <th3fanbus@gmail.com>2020-02-17 14:04:28 +0100
committerPatrick Georgi <pgeorgi@google.com>2020-03-15 13:04:39 +0000
commit31b7ee42016f7b54c24f30c271b4b93df16bfa10 (patch)
treeae4d33670204b4e09e228ff3d28385e76da7210d /src/include
parent95de2317c6c6379e43d3b3c27d34eb66198dbe0a (diff)
downloadcoreboot-31b7ee42016f7b54c24f30c271b4b93df16bfa10.tar.xz
treewide: Replace uses of "Nehalem"
The code in coreboot is actually for the Arrandale processors, which are a MCM (Multi-Chip Module) with two different dies: - Hillel: 32nm Westmere dual-core CPU - Ironlake: 45nm northbridge with integrated graphics This has nothing to do with the older, single-die Nehalem processors. Therefore, replace the references to Nehalem with the correct names. Change-Id: I8c10a2618c519d2411211b9b8f66d24f0018f908 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38942 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include')
-rw-r--r--src/include/cpu/intel/em64t101_save_state.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/include/cpu/intel/em64t101_save_state.h b/src/include/cpu/intel/em64t101_save_state.h
index 7493c85049..5d3f9edf9d 100644
--- a/src/include/cpu/intel/em64t101_save_state.h
+++ b/src/include/cpu/intel/em64t101_save_state.h
@@ -20,7 +20,7 @@
/* Intel Revision 30101 SMM State-Save Area
* The following processor architectures use this:
- * - Nehalem
+ * - Westmere
* - SandyBridge
* - IvyBridge
* - Haswell