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authorArthur Heymans <arthur@aheymans.xyz>2020-08-09 21:33:19 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-11-09 10:20:07 +0000
commit3967cf931b02414d4b420dcb43b4aeb5ce7d2430 (patch)
treedda5095618a5e9e2b1df562c6bcb0e343518d770 /src/include
parent7ac4722a35714bb02286a0ae0b47abaf1a35219d (diff)
downloadcoreboot-3967cf931b02414d4b420dcb43b4aeb5ce7d2430.tar.xz
cpu/x86/smm: Add a common save state handling
Currently coreboot has limited use for the SMM save state. Typically the only thing needed is to get or set a few registers and to know which CPU triggered the SMI (typically via an IO write). Abstracting away different SMM save states would allow to put some SMM functionality like the SMMSTORE entry in common places. To save place platforms can select different SMM save sate ops that should be implemented. For instance AMD platforms don't need Intel SMM save state handling. Some platforms can encounter CPUs with different save states, which the code then handles at runtime by comparing the SMM save state revision which is located at the same offset for all SMM save state types. Change-Id: I4a31d05c09065543424a9010ac434dde0dfb5836 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44323 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include')
-rw-r--r--src/include/cpu/x86/save_state.h34
1 files changed, 34 insertions, 0 deletions
diff --git a/src/include/cpu/x86/save_state.h b/src/include/cpu/x86/save_state.h
new file mode 100644
index 0000000000..d6fcf63d79
--- /dev/null
+++ b/src/include/cpu/x86/save_state.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __CPU_X86_SAVE_STATE_H__
+#define __CPU_X86_SAVE_STATE_H__
+
+#include <stdint.h>
+
+enum cpu_reg {
+ RAX,
+ RBX,
+ RCX,
+ RDX
+};
+
+#define SMM_REV_INVALID 0xffffffff
+
+struct smm_save_state_ops {
+ const uint32_t *revision_table;
+ /* Accessors for CPU registers in the SMM save state
+ Returns -1 on failure, 0 on success */
+ int (*get_reg)(const enum cpu_reg reg, const int node, void *out, const uint8_t length);
+ int (*set_reg)(const enum cpu_reg reg, const int node, void *in, const uint8_t length);
+ /* Returns -1 on failure, the node on which the 'cmd' was send on success */
+ int (*apmc_node)(u8 cmd);
+};
+
+/* Return -1 on failure, otherwise returns which CPU node issued an APMC IO write */
+int get_apmc_node(u8 cmd);
+/* Return -1 on failure, 0 on succes.
+ Accessors for the SMM save state CPU registers RAX, RBX, RCX and RDX */
+int get_save_state_reg(const enum cpu_reg reg, const int node, void *out, const uint8_t length);
+int set_save_state_reg(const enum cpu_reg reg, const int node, void *in, const uint8_t length);
+
+#endif /* __CPU_X86_SAVE_STATE_H__ */