diff options
author | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-07 15:00:18 -0800 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2017-03-12 15:45:37 +0100 |
commit | 84d20d0eb3869d7babaeed7cfbe53f9edad48850 (patch) | |
tree | 6a5d37792281c6c70d17ef925a250535bc236d9f /src/include | |
parent | 91d1e76fd168defce4132d1e308b68a2013a89df (diff) | |
download | coreboot-84d20d0eb3869d7babaeed7cfbe53f9edad48850.tar.xz |
src/include: Remove spaces before tabs
Fix the following warning detected by checkpatch.pl:
WARNING: please, no space before tabs
TEST=Build and run on Galileo Gen2
Change-Id: If60a58021d595289722d1d6064bea37b0b0bc039
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18652
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/include')
-rw-r--r-- | src/include/console/early_print.h | 6 | ||||
-rw-r--r-- | src/include/console/post_codes.h | 4 | ||||
-rw-r--r-- | src/include/console/uart.h | 2 | ||||
-rw-r--r-- | src/include/cpu/amd/gx2def.h | 2 | ||||
-rw-r--r-- | src/include/cpu/amd/lxdef.h | 6 | ||||
-rw-r--r-- | src/include/cpu/amd/vr.h | 82 | ||||
-rw-r--r-- | src/include/cpu/x86/lapic_def.h | 4 | ||||
-rw-r--r-- | src/include/cpu/x86/mtrr.h | 8 | ||||
-rw-r--r-- | src/include/device/device.h | 6 | ||||
-rw-r--r-- | src/include/device/pci_def.h | 10 | ||||
-rw-r--r-- | src/include/device/pci_ehci.h | 2 | ||||
-rw-r--r-- | src/include/device/pci_ids.h | 4 | ||||
-rw-r--r-- | src/include/pc80/i8259.h | 2 | ||||
-rw-r--r-- | src/include/pc80/mc146818rtc.h | 2 | ||||
-rw-r--r-- | src/include/reg_script.h | 2 | ||||
-rw-r--r-- | src/include/sdram_mode.h | 2 |
16 files changed, 72 insertions, 72 deletions
diff --git a/src/include/console/early_print.h b/src/include/console/early_print.h index bd125001d9..173b6feb96 100644 --- a/src/include/console/early_print.h +++ b/src/include/console/early_print.h @@ -28,9 +28,9 @@ #define console_log_level(msg_level) (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= msg_level) #define CALL_CONSOLE_TX(loglevel, tx_func, x) \ - do { \ - if (console_log_level(loglevel)) { \ - tx_func(x); \ + do { \ + if (console_log_level(loglevel)) { \ + tx_func(x); \ console_tx_flush(); \ } \ } while (0) diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index 9f24199cb7..e1a640cab7 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -63,7 +63,7 @@ * * POSTed before ramstage is about to be loaded into memory */ -#define POST_PREPARE_RAMSTAGE 0x11 +#define POST_PREPARE_RAMSTAGE 0x11 /** * \brief Copy/decompression finished; jumping to RAM @@ -341,7 +341,7 @@ * \n * Check the console output to see exactly where the failure occurred. */ -#define POST_DIE 0xff +#define POST_DIE 0xff /* diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 2c745dd0d4..45faf0ad6f 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -70,7 +70,7 @@ static inline void __uart_tx_flush(void) {} #endif #if CONFIG_GDB_STUB && (ENV_ROMSTAGE || ENV_RAMSTAGE) -#define CONFIG_UART_FOR_GDB CONFIG_UART_FOR_CONSOLE +#define CONFIG_UART_FOR_GDB CONFIG_UART_FOR_CONSOLE static inline void __gdb_hw_init(void) { uart_init(CONFIG_UART_FOR_GDB); } static inline void __gdb_tx_byte(u8 data) { uart_tx_byte(CONFIG_UART_FOR_GDB, data); } static inline void __gdb_tx_flush(void) { uart_tx_flush(CONFIG_UART_FOR_GDB); } diff --git a/src/include/cpu/amd/gx2def.h b/src/include/cpu/amd/gx2def.h index 2904857126..6a40d62e4b 100644 --- a/src/include/cpu/amd/gx2def.h +++ b/src/include/cpu/amd/gx2def.h @@ -32,7 +32,7 @@ /* GLCP_SYS_RSTPLL, Lower 32 bits */ #define GLCP_SYS_RSTPLL_SWFLAGS_SHIFT 26 -#define GLCP_SYS_RSTPLL_SWFLAGS_MASK (0x3f << 26) +#define GLCP_SYS_RSTPLL_SWFLAGS_MASK (0x3f << 26) #define GLCP_SYS_RSTPLL_LOCKWAIT 24 #define GLCP_SYS_RSTPLL_HOLDCOUNT 16 #define GLCP_SYS_RSTPLL_BYPASS 15 diff --git a/src/include/cpu/amd/lxdef.h b/src/include/cpu/amd/lxdef.h index 4865bea2ed..0d41c3b660 100644 --- a/src/include/cpu/amd/lxdef.h +++ b/src/include/cpu/amd/lxdef.h @@ -456,9 +456,9 @@ #define GLPCI_ARB_LOWER_VO2_SET (1 << 22) #define GLPCI_ARB_LOWER_OV1_SET (1 << 21) #define GLPCI_ARB_LOWER_OV0_SET (1 << 20) -#define GLPCI_ARB_LOWER_MSK2_SET (1<<18) -#define GLPCI_ARB_LOWER_MSK1_SET (1<<17) -#define GLPCI_ARB_LOWER_MSK0_SET (1<<16) +#define GLPCI_ARB_LOWER_MSK2_SET (1<<18) +#define GLPCI_ARB_LOWER_MSK1_SET (1<<17) +#define GLPCI_ARB_LOWER_MSK0_SET (1<<16) #define GLPCI_ARB_LOWER_CPRE_SET (1<<11) #define GLPCI_ARB_LOWER_PRE2_SET (1<<10) #define GLPCI_ARB_LOWER_PRE1_SET (1<<9) diff --git a/src/include/cpu/amd/vr.h b/src/include/cpu/amd/vr.h index 805b977cd7..e5ab840b58 100644 --- a/src/include/cpu/amd/vr.h +++ b/src/include/cpu/amd/vr.h @@ -35,20 +35,20 @@ #define PCI_INT_CD 0x0A // GPIO pins for INTC# and INTD# #define WATCHDOG 0x0B // Watchdog timer - #define MAX_MISC WATCHDOG + #define MAX_MISC WATCHDOG // NOTE: Do not change the order of the following registers: -#define VRC_AUDIO 0x01 // XpressAudio Class - #define AUDIO_VERSION 0x00 - #define PM_STATE 0x01 - #define SB_16_IO_BASE 0x02 - #define MIDI_BASE 0x03 - #define CPU_USAGE 0x04 - #define CODEC_TYPE 0x05 - #define STATE_INDEX 0x06 - #define STATE_DATA 0x07 - #define AUDIO_IRQ 0x08 // For use by native audio drivers +#define VRC_AUDIO 0x01 // XpressAudio Class + #define AUDIO_VERSION 0x00 + #define PM_STATE 0x01 + #define SB_16_IO_BASE 0x02 + #define MIDI_BASE 0x03 + #define CPU_USAGE 0x04 + #define CODEC_TYPE 0x05 + #define STATE_INDEX 0x06 + #define STATE_DATA 0x07 + #define AUDIO_IRQ 0x08 // For use by native audio drivers #define STATUS_PTR 0x09 // For use by native audio drivers #define MAX_AUDIO STATUS_PTR @@ -189,22 +189,22 @@ // SAA7127 - Not Used // ADV7300 - HDTV resolutions only // LO -> 720x480p - // MED -> 1280x720p + // MED -> 1280x720p // HI -> 1920x1080i - // FS454 - Both SD and HD resolutions - // SD Resolutions - NTSC and PAL + // FS454 - Both SD and HD resolutions + // SD Resolutions - NTSC and PAL // LO -> 640x480 - // MED -> 800x600 + // MED -> 800x600 // HI -> 1024x768 - // HD Resolutions + // HD Resolutions // LO -> 720x480p - // MED -> 1280x720p + // MED -> 1280x720p // HI -> 1920x1080i #define VG_TV_RES 0x0780 // TV resolution select mask #define VG_TV_RES_SHIFT 0x0007 // Right shift value #define VG_TV_RES_LO 0x0000 // Low resolution #define VG_TV_RES_MED 0x0080 // Medium resolution - #define VG_TV_RES_HI 0x0100 // High resolution + #define VG_TV_RES_HI 0x0100 // High resolution #define VG_TV_PASSTHRU 0x0800 // TV passthru mode #define VG_TV_SCALE_ADJ 0x05 // Modifies scaling factors for TV resolutions @@ -237,33 +237,33 @@ #define VG_FT_VESST 0x2C // Fixed timings, vertical sync start #define VG_FT_VESND 0x2D // Fixed timings, vertical sync end - #define MAX_VGA VGA_MEM_SIZE -// #define MAX_VG VG_FP_OPTION -// #define MAX_VG VG_START_OFFS_HI - #define MAX_VG VG_FT_VESND + #define MAX_VGA VGA_MEM_SIZE +// #define MAX_VG VG_FP_OPTION +// #define MAX_VG VG_START_OFFS_HI + #define MAX_VG VG_FT_VESND #define VRC_APM 0x03 #define REPORT_EVENT 0x00 - #define CAPABILITIES 0x01 + #define CAPABILITIES 0x01 #define APM_PRESENT 0x02 - #define MAX_APM APM_PRESENT + #define MAX_APM APM_PRESENT #define VRC_PM 0x04 // Legacy PM Class #define POWER_MODE 0x00 #define POWER_STATE 0x01 #define DOZE_TIMEOUT 0x02 - #define STANDBY_TIMEOUT 0x03 - #define SUSPEND_TIMEOUT 0x04 + #define STANDBY_TIMEOUT 0x03 + #define SUSPEND_TIMEOUT 0x04 #define PS2_TIMEOUT 0x05 #define RESUME_ON_RING 0x06 #define VIDEO_TIMEOUT 0x07 #define DISK_TIMEOUT 0x08 - #define FLOPPY_TIMEOUT 0x09 + #define FLOPPY_TIMEOUT 0x09 #define SERIAL_TIMEOUT 0x0A #define PARALLEL_TIMEOUT 0x0B - #define IRQ_WAKEUP_MASK 0x0C -// #define SUSPEND_MODULATION 0x0D + #define IRQ_WAKEUP_MASK 0x0C +// #define SUSPEND_MODULATION 0x0D #define SLEEP_PIN 0x0E #define SLEEP_PIN_ATTR 0x0F // #define SMI_WAKEUP_MASK 0x10 @@ -308,24 +308,24 @@ #define TV_CONTRAST 0x05 #define TV_OUTPUT 0x06 #define TV_TIMING 0x10 // 0x10...0x1D are all timings - #define MAX_TV TV_TIMING + #define MAX_TV TV_TIMING #define VRC_EXTERNAL_AMP 0x07 #define EAPD_VERSION 0x00 - #define AMP_POWER 0x01 + #define AMP_POWER 0x01 #define AMP_OFF 0x00 #define AMP_ON 0x01 #define AMP_TYPE 0x02 - #define MAX_EXTERNAL_AMP AMP_TYPE + #define MAX_EXTERNAL_AMP AMP_TYPE #define VRC_ACPI 0x08 #define ENABLE_ACPI 0x00 // Enable ACPI Mode - #define SCI_IRQ 0x01 // Set the IRQ the SCI is mapped to, sysbios use. + #define SCI_IRQ 0x01 // Set the IRQ the SCI is mapped to, sysbios use. #define ACPINVS_LO 0x02 // new calls to send 32bit physAddress of - #define ACPINVS_HI 0x03 // ACPI NVS region to VSA + #define ACPINVS_HI 0x03 // ACPI NVS region to VSA #define GLOBAL_LOCK 0x04 // read requests semaphore, write clears #define ACPI_UNUSED1 0x05 #define RW_PIRQ 0x06 // read/write PCI IRQ router regs in SB Func0 cfg space @@ -371,12 +371,12 @@ #define MAX_KEYBOARD MOUSE_XY -#define VRC_DDC 0x0D // Video DDC Class - #define VRC_DDC_ENABLE 0x00 // Enable/disable register +#define VRC_DDC 0x0D // Video DDC Class + #define VRC_DDC_ENABLE 0x00 // Enable/disable register #define DDC_DISABLE 0x00 - #define DDC_ENABLE 0x01 - #define VRC_DDC_IO 0x01 // A non-zero value for safety - #define MAX_DDC VRC_DDC_IO + #define DDC_ENABLE 0x01 + #define VRC_DDC_IO 0x01 // A non-zero value for safety + #define MAX_DDC VRC_DDC_IO #define VRC_DEBUGGER 0x0E #define MAX_DEBUGGER NO_VR @@ -399,7 +399,7 @@ #define VRC_OWL 0x11 // Virtual Register class #define VRC_OWL_DAC 0x00 // DAC (Backlight) Control - #define VRC_OWL_GPIO 0x01 // GPIO Control + #define VRC_OWL_GPIO 0x01 // GPIO Control #define MAX_OWL VRC_OWL_GPIO #define VRC_SYSINFO 0x12 // Virtual Register class @@ -472,7 +472,7 @@ #define VRC_THERMAL_SMB_DATA 0x09 #define MAX_THERMAL VRC_THERMAL_SMB_DATA -#define MAX_VR_CLASS VRC_THERMAL +#define MAX_VR_CLASS VRC_THERMAL /* * Write to a Virtual Register diff --git a/src/include/cpu/x86/lapic_def.h b/src/include/cpu/x86/lapic_def.h index ec1ca6e359..9da89ee873 100644 --- a/src/include/cpu/x86/lapic_def.h +++ b/src/include/cpu/x86/lapic_def.h @@ -21,7 +21,7 @@ #define LAPIC_RRR 0x0C0 #define LAPIC_SVR 0x0f0 #define LAPIC_SPIV 0x0f0 -#define LAPIC_SPIV_ENABLE 0x100 +#define LAPIC_SPIV_ENABLE 0x100 #define LAPIC_ESR 0x280 #define LAPIC_ESR_SEND_CS 0x00001 #define LAPIC_ESR_RECV_CS 0x00002 @@ -30,7 +30,7 @@ #define LAPIC_ESR_SENDILL 0x00020 #define LAPIC_ESR_RECVILL 0x00040 #define LAPIC_ESR_ILLREGA 0x00080 -#define LAPIC_ICR 0x300 +#define LAPIC_ICR 0x300 #define LAPIC_DEST_SELF 0x40000 #define LAPIC_DEST_ALLINC 0x80000 #define LAPIC_DEST_ALLBUT 0xC0000 diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 539c366c21..ddafc1eec3 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -25,12 +25,12 @@ #define SMRR_PHYS_BASE 0x1f2 #define SMRR_PHYS_MASK 0x1f3 -#define MTRR_PHYS_BASE(reg) (0x200 + 2 * (reg)) -#define MTRR_PHYS_MASK(reg) (MTRR_PHYS_BASE(reg) + 1) +#define MTRR_PHYS_BASE(reg) (0x200 + 2 * (reg)) +#define MTRR_PHYS_MASK(reg) (MTRR_PHYS_BASE(reg) + 1) #define MTRR_PHYS_MASK_VALID (1 << 11) -#define NUM_FIXED_RANGES 88 -#define RANGES_PER_FIXED_MTRR 8 +#define NUM_FIXED_RANGES 88 +#define RANGES_PER_FIXED_MTRR 8 #define MTRR_FIX_64K_00000 0x250 #define MTRR_FIX_16K_80000 0x258 #define MTRR_FIX_16K_A0000 0x259 diff --git a/src/include/device/device.h b/src/include/device/device.h index 6fcb9ae8a4..e60277d720 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -82,13 +82,13 @@ static inline void device_noop(struct device *dev) {} struct bus { - ROMSTAGE_CONST struct device * dev; /* This bridge device */ - ROMSTAGE_CONST struct device * children; /* devices behind this bridge */ + ROMSTAGE_CONST struct device * dev; /* This bridge device */ + ROMSTAGE_CONST struct device * children; /* devices behind this bridge */ ROMSTAGE_CONST struct bus *next; /* The next bridge on this device */ unsigned int bridge_ctrl; /* Bridge control register */ uint16_t bridge_cmd; /* Bridge command register */ unsigned char link_num; /* The index of this link */ - uint16_t secondary; /* secondary bus number */ + uint16_t secondary; /* secondary bus number */ uint16_t subordinate; /* max subordinate bus number */ unsigned char cap; /* PCi capability offset */ uint32_t hcdn_reg; /* For HyperTransport link */ diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index e11470c695..a1236eff2d 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -15,7 +15,7 @@ #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ -#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ +#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ #define PCI_COMMAND_INT_DISABLE 0x400 /* Interrupt disable */ @@ -183,7 +183,7 @@ #define PCI_CAP_ID_PCIX 0x07 /* PCIX */ #define PCI_CAP_ID_HT 0x08 /* Hypertransport */ #define PCI_CAP_ID_EHCI_DEBUG 0x0A /* EHCI debug port */ -#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ +#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ #define PCI_CAP_ID_PCIE 0x10 /* PCI Express */ #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ @@ -243,8 +243,8 @@ #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ -#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ -#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ +#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ +#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */ #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */ @@ -289,7 +289,7 @@ #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ #define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */ #define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */ -#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ +#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ #define PCI_X_STATUS 4 /* PCI-X capabilities */ #define PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */ #define PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */ diff --git a/src/include/device/pci_ehci.h b/src/include/device/pci_ehci.h index 42e1d8365f..4a89a60852 100644 --- a/src/include/device/pci_ehci.h +++ b/src/include/device/pci_ehci.h @@ -21,7 +21,7 @@ #include <device/device.h> #define EHCI_BAR_INDEX 0x10 -#define PCI_EHCI_CLASSCODE 0x0c0320 /* USB2.0 with EHCI controller */ +#define PCI_EHCI_CLASSCODE 0x0c0320 /* USB2.0 with EHCI controller */ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx); u8 *pci_ehci_base_regs(pci_devfn_t dev); diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 7d59415931..023238753f 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -598,7 +598,7 @@ #define PCI_DEVICE_ID_AMD_8111_IDE 0x7469 #define PCI_DEVICE_ID_AMD_8111_SMB 0x746a #define PCI_DEVICE_ID_AMD_8111_ACPI 0x746b -#define PCI_DEVICE_ID_AMD_8111_NIC 0x7462 +#define PCI_DEVICE_ID_AMD_8111_NIC 0x7462 #define PCI_DEVICE_ID_AMD_8111_USB2 0x7463 #define PCI_DEVICE_ID_AMD_8131_PCIX 0x7450 @@ -2743,7 +2743,7 @@ #define PCI_DEVICE_ID_MICROGATE_SCA 0x0030 #define PCI_VENDOR_ID_SIS 0x1039 -#define PCI_DEVICE_ID_SIS_AGP 0x0002 +#define PCI_DEVICE_ID_SIS_AGP 0x0002 /* SiS 761GX NORTH BRIDGE */ #define PCI_DEVICE_ID_SIS_SIS761 0x0761 diff --git a/src/include/pc80/i8259.h b/src/include/pc80/i8259.h index ea6637ed11..857c5c88b2 100644 --- a/src/include/pc80/i8259.h +++ b/src/include/pc80/i8259.h @@ -69,7 +69,7 @@ #define SLAVE_PIC_ICW3 0xa1 #define SLAVE_ID 0x02 -#define MASTER_PIC_OCW1 0x21 +#define MASTER_PIC_OCW1 0x21 #define SLAVE_PIC_OCW1 0xa1 #define IRQ2 (1 << 2) #define ALL_IRQS 0xff diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 9f4eb5adbe..39f58d6015 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -41,7 +41,7 @@ # define RTC_DIV_RESET1 0x60 # define RTC_DIV_RESET2 0x70 /* Periodic intr. / Square wave rate select. 0 = none, 1 = 32.8kHz,... 15 = 2Hz */ -# define RTC_RATE_SELECT 0x0F +# define RTC_RATE_SELECT 0x0F # define RTC_RATE_NONE 0x00 # define RTC_RATE_32786HZ 0x01 # define RTC_RATE_16384HZ 0x02 diff --git a/src/include/reg_script.h b/src/include/reg_script.h index d1e0e1a2dc..3d8b72b2c5 100644 --- a/src/include/reg_script.h +++ b/src/include/reg_script.h @@ -110,7 +110,7 @@ struct reg_script_bus_entry { #define REG_SCRIPT_TABLE_ATTRIBUTE __attribute__ ((used, section (".rsbe_init"))) #define REG_SCRIPT_BUS_ENTRY(bus_entry_) \ - const struct reg_script_bus_entry *rsbe_ ## bus_entry_ \ + const struct reg_script_bus_entry *rsbe_ ## bus_entry_ \ REG_SCRIPT_TABLE_ATTRIBUTE = &bus_entry_; /* Internal helper Macros. */ diff --git a/src/include/sdram_mode.h b/src/include/sdram_mode.h index 3b2facaa5d..78002b7031 100644 --- a/src/include/sdram_mode.h +++ b/src/include/sdram_mode.h @@ -50,4 +50,4 @@ #define SDRAM_EXTMODE_DRIVE_NORMAL (0 << 1) #define SDRAM_EXTMODE_DRIVE_WEAK (1 << 1) /* Optional */ -#endif // __SDRAMMODE_H_DEFINED +#endif // __SDRAMMODE_H_DEFINED |