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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-07-20 23:41:54 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-07-30 19:03:27 +0000 |
| commit | 06f818c932be5e19176db0d50939ee89da3267ad (patch) | |
| tree | 9865fb6b53caeb4535b36c0a9375144797c4edc0 /src/include | |
| parent | e8d0c0092a71c5890a1dfbdc7b941dc5e05b0501 (diff) | |
| download | coreboot-06f818c932be5e19176db0d50939ee89da3267ad.tar.xz | |
cpu/intel/smm/gen1: Use correct MSR for model_6fx and model_1067x
According to the "Intel® 64 and IA-32 Architectures Software Developer’s Manual"
the SMRR MSR are at a different offset for model_6fx and model_1067x.
This still need SMRR enabled and lock bit set in MSR_FEATURE_CONTROL.
Change-Id: I8ee8292ab038e58deb8c24745ec1a9b5da8c31a9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/cpu/x86/mtrr.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index a4f1f888e3..1f704ac869 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -31,6 +31,10 @@ #define IA32_SMRR_PHYS_BASE 0x1f2 #define IA32_SMRR_PHYS_MASK 0x1f3 +/* Specific to model_6fx and model_1067x */ +#define MSR_SMRR_PHYS_BASE 0xa0 +#define MSR_SMRR_PHYS_MASK 0xa1 + #define MTRR_PHYS_BASE(reg) (0x200 + 2 * (reg)) #define MTRR_PHYS_MASK(reg) (MTRR_PHYS_BASE(reg) + 1) #define MTRR_PHYS_MASK_VALID (1 << 11) |