diff options
| author | Kenji Chen <kenji.chen@intel.com> | 2014-10-04 01:14:44 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-03-23 13:11:15 +0100 |
| commit | 31c6e632cf607ad8364c49b934f726ef02486d46 (patch) | |
| tree | dc4a40bf1f4358719837141d4a9044304fcf03d9 /src/include | |
| parent | 431e51ec2aeb739504bbb09c342091d407fa8ca1 (diff) | |
| download | coreboot-31c6e632cf607ad8364c49b934f726ef02486d46.tar.xz | |
PCIe: Add L1 Sub-State support.
Enable L1 Sub-State when both root port and endpoint support it.
[pg: keyed the feature to MMCONF_SUPPORT, otherwise boards
without that capability fail to build.]
Change-Id: Id11fc7c73eb865411747eef63f5f901e00a17f84
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6ac04ad7e2261846e40da297f7fa317ccebda092
Original-BUG=chrome-os-partner:31424
Original-TEST=Build a image and run on Samus proto boards to check if the
settings are applied correctly. I just only have proto boards and
need someone having EVT boards to confirm the settings.
Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Original-Change-Id: Id1b5a52ff0b896f4531c4a6e68e70a2cea8c736a
Original-Reviewed-on: https://chromium-review.googlesource.com/221436
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/8832
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/device/pci.h | 1 | ||||
| -rw-r--r-- | src/include/device/pci_def.h | 6 | ||||
| -rw-r--r-- | src/include/device/pciexp.h | 1 |
3 files changed, 8 insertions, 0 deletions
diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 0670da4822..4e712f9f7b 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -33,6 +33,7 @@ struct pci_operations { /* set the Subsystem IDs for the PCI device */ void (*set_subsystem)(device_t dev, unsigned vendor, unsigned device); + void (*set_L1_ss_latency)(device_t dev, unsigned int off); }; /* Common pci bus operations */ diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index 403978584d..c49e4ebf36 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -405,6 +405,12 @@ #define PCI_EXT_CAP_ID_DSN 3 #define PCI_EXT_CAP_ID_PWR 4 +/* Extended Capability lists*/ +#define PCIE_EXT_CAP_OFFSET 0x100 +#define PCIE_EXT_CAP_AER_ID 0x0001 +#define PCIE_EXT_CAP_L1SS_ID 0x001E +#define PCIE_EXT_CAP_LTR_ID 0x0018 + /* Advanced Error Reporting */ #define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */ #define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */ diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h index 87a5002c5e..1146557858 100644 --- a/src/include/device/pciexp.h +++ b/src/include/device/pciexp.h @@ -15,4 +15,5 @@ unsigned int pciexp_scan_bridge(device_t dev, unsigned int max); extern struct device_operations default_pciexp_ops_bus; +unsigned int pciexp_find_extended_cap(device_t dev, unsigned int cap); #endif /* DEVICE_PCIEXP_H */ |