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authorHannah Williams <hannah.williams@intel.com>2017-05-13 15:59:15 -0700
committerAaron Durbin <adurbin@chromium.org>2017-05-22 21:29:55 +0200
commit240409a5f69f04d406e99cf954fb50a024ec84a1 (patch)
tree90ba7114e5ea76dd799796d1760e78d77397fdad /src/include
parent7941c96f8eaeb35179b30283ef7bfab6929f2bb7 (diff)
downloadcoreboot-240409a5f69f04d406e99cf954fb50a024ec84a1.tar.xz
include/device: Add pci ids for Intel GLK
Change-Id: Ifbca20a0c38cc1fb8ee4b4e336d59e834fcaf57a Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/19686 Reviewed-by: Brenton Dong <brenton.m.dong@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include')
-rw-r--r--src/include/device/pci_ids.h24
1 files changed, 24 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 5a2e1b299f..da6cd8c39a 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -2672,6 +2672,7 @@
#define PCI_DEVICE_ID_INTEL_KBP_LP_U_PREMIUM 0x9d58
#define PCI_DEVICE_ID_INTEL_KBP_LP_Y_PREMIUM 0x9d56
#define PCI_DEVICE_ID_INTEL_APL_LPC 0x5ae8
+#define PCI_DEVICE_ID_INTEL_GLK_LPC 0x31e8
/* Intel PCIE device ids */
#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 0x9d10
@@ -2738,11 +2739,13 @@
#define PCI_DEVICE_ID_INTEL_SPT_U_Y_PREMIUM_SATA 0x9d07
#define PCI_DEVICE_ID_INTEL_SPT_KBL_SATA 0x282a
#define PCI_DEVICE_ID_INTEL_APL_SATA 0x5ae0
+#define PCI_DEVICE_ID_INTEL_GLK_SATA 0x31e3
/* Intel PMC device Ids */
#define PCI_DEVICE_ID_INTEL_SPT_LP_PMC 0x9d21
#define PCI_DEVICE_ID_INTEL_KBP_H_PMC 0xa121
#define PCI_DEVICE_ID_INTEL_APL_PMC 0x5a94
+#define PCI_DEVICE_ID_INTEL_GLK_PMC 0x3194
/* Intel I2C device Ids */
#define PCI_DEVICE_ID_INTEL_SPT_I2C0 0x9d60
@@ -2759,6 +2762,14 @@
#define PCI_DEVICE_ID_INTEL_APL_I2C5 0x5ab6
#define PCI_DEVICE_ID_INTEL_APL_I2C6 0x5ab8
#define PCI_DEVICE_ID_INTEL_APL_I2C7 0x5aba
+#define PCI_DEVICE_ID_INTEL_GLK_I2C0 0x31ac
+#define PCI_DEVICE_ID_INTEL_GLK_I2C1 0x31ae
+#define PCI_DEVICE_ID_INTEL_GLK_I2C2 0x31b0
+#define PCI_DEVICE_ID_INTEL_GLK_I2C3 0x31b2
+#define PCI_DEVICE_ID_INTEL_GLK_I2C4 0x31b4
+#define PCI_DEVICE_ID_INTEL_GLK_I2C5 0x31b6
+#define PCI_DEVICE_ID_INTEL_GLK_I2C6 0x31b8
+#define PCI_DEVICE_ID_INTEL_GLK_I2C7 0x31ba
/* Intel UART device Ids */
#define PCI_DEVICE_ID_INTEL_SPT_UART0 0x9d27
@@ -2771,6 +2782,10 @@
#define PCI_DEVICE_ID_INTEL_APL_UART1 0x5abe
#define PCI_DEVICE_ID_INTEL_APL_UART2 0x5ac0
#define PCI_DEVICE_ID_INTEL_APL_UART3 0x5aee
+#define PCI_DEVICE_ID_INTEL_GLK_UART0 0x31bc
+#define PCI_DEVICE_ID_INTEL_GLK_UART1 0x31be
+#define PCI_DEVICE_ID_INTEL_GLK_UART2 0x31c0
+#define PCI_DEVICE_ID_INTEL_GLK_UART3 0x31ee
/* Intel SPI device Ids */
#define PCI_DEVICE_ID_INTEL_SPT_SPI1 0x9d24
@@ -2780,6 +2795,9 @@
#define PCI_DEVICE_ID_INTEL_APL_SPI1 0x5ac4
#define PCI_DEVICE_ID_INTEL_APL_SPI2 0x5ac6
#define PCI_DEVICE_ID_INTEL_APL_HWSEQ_SPI 0x5a96
+#define PCI_DEVICE_ID_INTEL_GLK_SPI0 0x31c2
+#define PCI_DEVICE_ID_INTEL_GLK_SPI1 0x31c4
+#define PCI_DEVICE_ID_INTEL_GLK_SPI2 0x31c6
/* Intel IGD device Ids */
#define PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM 0x1906
@@ -2794,9 +2812,11 @@
#define PCI_DEVICE_ID_INTEL_KBL_GT2_SHALM 0x591B
#define PCI_DEVICE_ID_INTEL_APL_IGD_HD_505 0x5a84
#define PCI_DEVICE_ID_INTEL_APL_IGD_HD_500 0x5a85
+#define PCI_DEVICE_ID_INTEL_GLK_IGD 0x3184
/* Intel Northbridge Ids */
#define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0
+#define PCI_DEVICE_ID_INTEL_GLK_NB 0x31f0
/* Intel SMBUS device Ids */
#define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23
@@ -2810,15 +2830,19 @@
/* Intel P2SB device Ids */
#define PCI_DEVICE_ID_INTEL_APL_P2SB 0x5a92
+#define PCI_DEVICE_ID_INTEL_GLK_P2SB 0x3192
/* Intel SRAM device Ids */
#define PCI_DEVICE_ID_INTEL_APL_SRAM 0x5aec
+#define PCI_DEVICE_ID_INTEL_GLK_SRAM 0x31ec
/* Intel AUDIO device Ids */
#define PCI_DEVICE_ID_INTEL_APL_AUDIO 0x5a98
+#define PCI_DEVICE_ID_INTEL_GLK_AUDIO 0x3198
/* Intel HECI/ME device Ids */
#define PCI_DEVICE_ID_INTEL_APL_CSE0 0x5a9a
+#define PCI_DEVICE_ID_INTEL_GLK_CSE0 0x319a
/* Intel XDCI device Ids */
#define PCI_DEVICE_ID_INTEL_APL_XDCI 0x5aaa