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authorArthur Heymans <arthur@aheymans.xyz>2017-06-15 19:07:12 +0200
committerMartin Roth <martinroth@google.com>2017-06-22 15:21:49 +0000
commit2721e1fab72111c28267d8b74a71c66abd887a2f (patch)
tree2b890c939d10162b2523c69510bc22be4ddb4b5d /src/include
parent58d16af91862a964db24b575b9110c767a975916 (diff)
downloadcoreboot-2721e1fab72111c28267d8b74a71c66abd887a2f.tar.xz
device/dram/ddr3.h: Add brackets around macro
This fixes improper dram frequency being displayed in sandy bridge native raminit. Change-Id: I1fe4e4331f45ce1c21113c039b8433252326293d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src/include')
-rw-r--r--src/include/device/dram/ddr3.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h
index 5961f4106b..2cfd6acbff 100644
--- a/src/include/device/dram/ddr3.h
+++ b/src/include/device/dram/ddr3.h
@@ -52,7 +52,7 @@
* These values are in 1/256 ns units.
* @{
*/
-#define NS2MHZ_DIV256 1000 << 8
+#define NS2MHZ_DIV256 (1000 << 8)
#define TCK_1333MHZ 192
#define TCK_1200MHZ 212