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authorLean Sheng Tan <lean.sheng.tan@intel.com>2019-05-27 13:06:35 +0800
committerPhilipp Deppenwiese <zaolin.daisuki@gmail.com>2019-07-17 14:28:41 +0000
commit38c3ff7b6ef2875b789d9621363db9165b9a1078 (patch)
treef13e8f98cac2ae0e260e2100c94d4f60d1420109 /src/include
parentf2ac0137566076262152f74b6b6761c9f6f2def2 (diff)
downloadcoreboot-38c3ff7b6ef2875b789d9621363db9165b9a1078.tar.xz
soc/intel/cannonlake: Add device Ids for new CFL SKUs support
- Add CPU, MCH & IGD IDs for new Coffeelake SKUs - Add PCH, LPC, SPI IDs for CNP-H PCH CM246 & C246 - Make some minor alignments & naming corrections to align with the rest TEST= build, boot to both Linux & windows OS on CFL H & S platforms and verified all the device Id's in serial console logs. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I343b11ea8d9c33eb189d7478511a473b145f4ab4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/include')
-rw-r--r--src/include/device/pci_ids.h90
1 files changed, 50 insertions, 40 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 0c846c64d9..d014e58a1e 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -2730,6 +2730,7 @@
#define PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC 0x9d83
#define PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370 0xa306
#define PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370 0xa30c
+#define PCI_DEVICE_ID_INTEL_CNP_H_LPC_C246 0xa309
#define PCI_DEVICE_ID_INTEL_CNP_H_LPC_CM246 0xa30e
#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI 0x3480
#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI_REV0 0x3481
@@ -3002,6 +3003,10 @@
#define PCI_DEVICE_ID_INTEL_CNL_SPI1 0x9dab
#define PCI_DEVICE_ID_INTEL_CNL_SPI2 0x9dfb
#define PCI_DEVICE_ID_INTEL_CNL_HWSEQ_SPI 0x9da4
+#define PCI_DEVICE_ID_INTEL_CNP_H_SPI0 0xa32a
+#define PCI_DEVICE_ID_INTEL_CNP_H_SPI1 0xa32b
+#define PCI_DEVICE_ID_INTEL_CNP_H_SPI2 0xa37b
+#define PCI_DEVICE_ID_INTEL_CNP_H_HWSEQ_SPI 0xa324
#define PCI_DEVICE_ID_INTEL_ICP_SPI0 0x34aa
#define PCI_DEVICE_ID_INTEL_ICP_SPI1 0x34ab
#define PCI_DEVICE_ID_INTEL_ICP_SPI2 0x34fb
@@ -3042,11 +3047,13 @@
#define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4 0x5A4A
#define PCI_DEVICE_ID_INTEL_CFL_GT2_ULT 0x3EA5
#define PCI_DEVICE_ID_INTEL_CFL_H_GT2 0x3e9b
-#define PCI_DEVICE_ID_INTEL_CFL_S_GT2 0x3e92
#define PCI_DEVICE_ID_INTEL_CFL_H_XEON_GT2 0x3e94
-#define PCI_DEVICE_ID_INTEL_ICL_GT0_ULT 0x8A70
+#define PCI_DEVICE_ID_INTEL_CFL_S_GT2_1 0x3e92
+#define PCI_DEVICE_ID_INTEL_CFL_S_GT2_2 0x3e98
+#define PCI_DEVICE_ID_INTEL_CFL_S_GT2_3 0x3e9a
+#define PCI_DEVICE_ID_INTEL_ICL_GT0_ULT 0x8A70
#define PCI_DEVICE_ID_INTEL_ICL_GT0_5_ULT 0x8A71
-#define PCI_DEVICE_ID_INTEL_ICL_GT1_ULT 0x8A40
+#define PCI_DEVICE_ID_INTEL_ICL_GT1_ULT 0x8A40
#define PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_0 0x8A50
#define PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_1 0x8A5D
#define PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_1 0x8A5B
@@ -3059,7 +3066,7 @@
#define PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_5 0x8A55
#define PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_5 0x8A56
#define PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_6 0x8A57
-#define PCI_DEVICE_ID_INTEL_ICL_GT3_ULT 0x8A62
+#define PCI_DEVICE_ID_INTEL_ICL_GT3_ULT 0x8A62
#define PCI_DEVICE_ID_INTEL_CML_GT1_ULT_1 0x9B21
#define PCI_DEVICE_ID_INTEL_CML_GT1_ULT_2 0x9B2A
#define PCI_DEVICE_ID_INTEL_CML_GT2_ULT_1 0x9B41
@@ -3080,43 +3087,46 @@
#define PCI_DEVICE_ID_INTEL_CML_GT2_H_2 0x9B42
/* Intel Northbridge Ids */
-#define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0
-#define PCI_DEVICE_ID_INTEL_GLK_NB 0x31f0
-#define PCI_DEVICE_ID_INTEL_SKL_ID_U 0x1904
-#define PCI_DEVICE_ID_INTEL_SKL_ID_Y 0x190c
-#define PCI_DEVICE_ID_INTEL_SKL_ID_ULX 0x1924
-#define PCI_DEVICE_ID_INTEL_SKL_ID_H_2 0x1900
-#define PCI_DEVICE_ID_INTEL_SKL_ID_H 0x1910
-#define PCI_DEVICE_ID_INTEL_SKL_ID_S_2 0x190f
-#define PCI_DEVICE_ID_INTEL_SKL_ID_S_4 0x191f
-#define PCI_DEVICE_ID_INTEL_KBL_ID_S 0x590f
-#define PCI_DEVICE_ID_INTEL_SKL_ID_H_EM 0x1918
-#define PCI_DEVICE_ID_INTEL_SKL_ID_DT 0x191f
-#define PCI_DEVICE_ID_INTEL_KBL_ID_U 0x5904
-#define PCI_DEVICE_ID_INTEL_KBL_ID_Y 0x590c
-#define PCI_DEVICE_ID_INTEL_KBL_ID_H 0x5910
-#define PCI_DEVICE_ID_INTEL_KBL_U_R 0x5914
-#define PCI_DEVICE_ID_INTEL_KBL_ID_DT_2 0x5918
-#define PCI_DEVICE_ID_INTEL_KBL_ID_DT 0x591f
-#define PCI_DEVICE_ID_INTEL_CNL_ID_U 0x5A04
-#define PCI_DEVICE_ID_INTEL_CNL_ID_Y 0x5A02
-#define PCI_DEVICE_ID_INTEL_WHL_ID_Wx4 0x3E34
-#define PCI_DEVICE_ID_INTEL_WHL_ID_Wx2 0x3E35
-#define PCI_DEVICE_ID_INTEL_CFL_ID_U 0x3ED0
-#define PCI_DEVICE_ID_INTEL_CFL_ID_H 0x3ec4
-#define PCI_DEVICE_ID_INTEL_CFL_ID_S 0x3ec2
-#define PCI_DEVICE_ID_INTEL_ICL_ID_U 0x8A12
+#define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0
+#define PCI_DEVICE_ID_INTEL_GLK_NB 0x31f0
+#define PCI_DEVICE_ID_INTEL_SKL_ID_U 0x1904
+#define PCI_DEVICE_ID_INTEL_SKL_ID_Y 0x190c
+#define PCI_DEVICE_ID_INTEL_SKL_ID_ULX 0x1924
+#define PCI_DEVICE_ID_INTEL_SKL_ID_H_2 0x1900
+#define PCI_DEVICE_ID_INTEL_SKL_ID_H 0x1910
+#define PCI_DEVICE_ID_INTEL_SKL_ID_S_2 0x190f
+#define PCI_DEVICE_ID_INTEL_SKL_ID_S_4 0x191f
+#define PCI_DEVICE_ID_INTEL_KBL_ID_S 0x590f
+#define PCI_DEVICE_ID_INTEL_SKL_ID_H_EM 0x1918
+#define PCI_DEVICE_ID_INTEL_SKL_ID_DT 0x191f
+#define PCI_DEVICE_ID_INTEL_KBL_ID_U 0x5904
+#define PCI_DEVICE_ID_INTEL_KBL_ID_Y 0x590c
+#define PCI_DEVICE_ID_INTEL_KBL_ID_H 0x5910
+#define PCI_DEVICE_ID_INTEL_KBL_U_R 0x5914
+#define PCI_DEVICE_ID_INTEL_KBL_ID_DT_2 0x5918
+#define PCI_DEVICE_ID_INTEL_KBL_ID_DT 0x591f
+#define PCI_DEVICE_ID_INTEL_CNL_ID_U 0x5A04
+#define PCI_DEVICE_ID_INTEL_CNL_ID_Y 0x5A02
+#define PCI_DEVICE_ID_INTEL_WHL_ID_W_4 0x3E34
+#define PCI_DEVICE_ID_INTEL_WHL_ID_W_2 0x3E35
+#define PCI_DEVICE_ID_INTEL_CFL_ID_U 0x3ED0
+#define PCI_DEVICE_ID_INTEL_CFL_ID_H 0x3ec4
+#define PCI_DEVICE_ID_INTEL_CFL_ID_H_8 0x3e20
+#define PCI_DEVICE_ID_INTEL_CFL_ID_S 0x3ec2
+#define PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8 0x3e30
+#define PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_8 0x3e31
+#define PCI_DEVICE_ID_INTEL_ICL_ID_U 0x8A12
#define PCI_DEVICE_ID_INTEL_ICL_ID_U_2_2 0x8A02
-#define PCI_DEVICE_ID_INTEL_ICL_ID_Y 0x8A10
-#define PCI_DEVICE_ID_INTEL_ICL_ID_Y_2 0x8A00
-#define PCI_DEVICE_ID_INTEL_CML_ULT 0x9B61
-#define PCI_DEVICE_ID_INTEL_CML_ULT_2_2 0x9B71
-#define PCI_DEVICE_ID_INTEL_CML_ULT_6_2 0x9B51
-#define PCI_DEVICE_ID_INTEL_CML_ULX 0x9B60
-#define PCI_DEVICE_ID_INTEL_CML_S 0x9B55
-#define PCI_DEVICE_ID_INTEL_CML_S_10_2 0x9B35
-#define PCI_DEVICE_ID_INTEL_CML_H 0x9B54
-#define PCI_DEVICE_ID_INTEL_CML_H_8_2 0x9B44
+#define PCI_DEVICE_ID_INTEL_ICL_ID_Y 0x8A10
+#define PCI_DEVICE_ID_INTEL_ICL_ID_Y_2 0x8A00
+#define PCI_DEVICE_ID_INTEL_CML_ULT 0x9B61
+#define PCI_DEVICE_ID_INTEL_CML_ULT_2_2 0x9B71
+#define PCI_DEVICE_ID_INTEL_CML_ULT_6_2 0x9B51
+#define PCI_DEVICE_ID_INTEL_CML_ULX 0x9B60
+#define PCI_DEVICE_ID_INTEL_CML_S 0x9B55
+#define PCI_DEVICE_ID_INTEL_CML_S_10_2 0x9B35
+#define PCI_DEVICE_ID_INTEL_CML_H 0x9B54
+#define PCI_DEVICE_ID_INTEL_CML_H_8_2 0x9B44
/* Intel SMBUS device Ids */
#define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23