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authorTim Wawrzynczak <twawrzynczak@chromium.org>2020-09-01 16:08:02 -0600
committerPatrick Georgi <pgeorgi@google.com>2020-09-08 05:24:42 +0000
commit62669a24eaf5236a60eebf8e26eefc984ca321ee (patch)
treed28d15f4e71cd3fb481aa4f73438460c4e49031a /src/include
parent7f844ab8b710e3244d1e681e800d99163cc9c65f (diff)
downloadcoreboot-62669a24eaf5236a60eebf8e26eefc984ca321ee.tar.xz
cpu/x86: Add definition for SMRR_PHYS_MASK_LOCK
The IA32_SMRR_PHYS_MASK MSR contains a 'Lock' bit, which will cause the core to generate a #GP if the SMRR_BASE or SMRR_MASK registers are written to after the Lock bit is set; this is helpful with securing SMM. BUG=b:164489598 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I784d1d1abec0a0fe0ee267118d084ac594a51647 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/include')
-rw-r--r--src/include/cpu/x86/mtrr.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 42964b02ea..6e30199c5f 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -30,6 +30,7 @@
#define IA32_SMRR_PHYS_BASE 0x1f2
#define IA32_SMRR_PHYS_MASK 0x1f3
+#define SMRR_PHYS_MASK_LOCK (1 << 10)
/* Specific to model_6fx and model_1067x */
#define MSR_SMRR_PHYS_BASE 0xa0