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authorSubrata Banik <subrata.banik@intel.com>2020-08-08 12:39:49 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-08-10 06:30:39 +0000
commitc56b90703f68c6c77fa876b910c0082b611b7471 (patch)
treec4e813e234cd385acbc6bd803f6f5f3451a3250f /src/include
parent8aa86c9c1b630d4a3b635ccedf0e144b217597f9 (diff)
downloadcoreboot-c56b90703f68c6c77fa876b910c0082b611b7471.tar.xz
soc/intel/common: Include Alder Lake SATA controller device IDs
Document Number: 619501, 619362 Change-Id: Id3440b415ca80edebb6880b8b48f6094ebea4ae4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/include')
-rw-r--r--src/include/device/pci_ids.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 05900da348..589e50cb90 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -3276,6 +3276,18 @@
#define PCI_DEVICE_ID_INTEL_MCC_AHCI_SATA 0x4b60
#define PCI_DEVICE_ID_INTEL_JSP_SATA_1 0x4dd2
#define PCI_DEVICE_ID_INTEL_JSP_SATA_2 0x4dd3
+#define PCI_DEVICE_ID_INTEL_ADP_P_SATA_1 0x7a52
+#define PCI_DEVICE_ID_INTEL_ADP_P_SATA_2 0x7a53
+#define PCI_DEVICE_ID_INTEL_ADP_P_SATA_3 0x7a54
+#define PCI_DEVICE_ID_INTEL_ADP_P_SATA_4 0x7a55
+#define PCI_DEVICE_ID_INTEL_ADP_P_SATA_5 0x7a56
+#define PCI_DEVICE_ID_INTEL_ADP_P_SATA_6 0x7a57
+#define PCI_DEVICE_ID_INTEL_ADP_S_SATA_1 0x7ae2
+#define PCI_DEVICE_ID_INTEL_ADP_S_SATA_2 0x7ae3
+#define PCI_DEVICE_ID_INTEL_ADP_S_SATA_3 0x7ae4
+#define PCI_DEVICE_ID_INTEL_ADP_S_SATA_4 0x7ae5
+#define PCI_DEVICE_ID_INTEL_ADP_S_SATA_5 0x7ae6
+#define PCI_DEVICE_ID_INTEL_ADP_S_SATA_6 0x7ae7
/* Intel PMC device Ids */
#define PCI_DEVICE_ID_INTEL_SPT_LP_PMC 0x9d21