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| author | Vadim Bendebury <vbendeb@chromium.org> | 2014-11-29 15:06:26 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-13 13:01:33 +0200 |
| commit | f9ff353430aae70e5cc04fb32d983b572956bd7d (patch) | |
| tree | bd8e41ccc824d0510e6872063b769ab4d6ab7fdf /src/include | |
| parent | 038cce2c2ec540163563a42c784f1c32564ee1b4 (diff) | |
| download | coreboot-f9ff353430aae70e5cc04fb32d983b572956bd7d.tar.xz | |
spi: support controllers with limited transfer size capabilities
Some SPI controllers (like Imgtec Pistachio), have a hard limit on SPI
read and write transactions. Limiting transfer size in the wrapper
allows to provide the API user with unlimited transfer size
transactions.
The tranfer size limitation is added to the spi_slave structure, which
is set up by the controller driver. The value of zero in this field
means 'unlimited transfer size'. It will work with existion drivers,
as they all either keep structures in the bss segment, or initialize
them to all zeros.
This patch addresses the problem for reads only, as coreboot is not
expected to require to write long chunks into SPI devices.
BRANCH=none
BUG=chrome-os-partner:32441, chrome-os-partner:31438
TEST=set transfer size limit to artificially low value (4K) and
observed proper operation on both Pistachio and ipq8086: both
Storm and Urara booted through romstage and ramstage.
Change-Id: Ibb96aa499c3eec458c94bf1193fbbbf5f54e1477
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 4f064fdca5b6c214e7a7f2751dc24e33cac2ea45
Original-Change-Id: I9df24f302edc872bed991ea450c0af33a1c0ff7b
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/232239
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9571
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/spi-generic.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/include/spi-generic.h b/src/include/spi-generic.h index bd0020f5d2..4de138cf09 100644 --- a/src/include/spi-generic.h +++ b/src/include/spi-generic.h @@ -43,11 +43,16 @@ * bus: ID of the bus that the slave is attached to. * cs: ID of the chip select connected to the slave. * rw: Read or Write flag + * max_transfer_size: maximum amount of bytes which can be sent in a single + * read or write transaction, usually this is a controller + * property, kept in the slave structure for convenience. Zero in + * this field means 'unlimited'. */ struct spi_slave { unsigned int bus; unsigned int cs; unsigned int rw; + unsigned int max_transfer_size; int force_programmer_specific; struct spi_flash * (*programmer_specific_probe) (struct spi_slave *spi); }; |