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authorRaul E Rangel <rrangel@chromium.org>2020-06-04 16:42:50 -0600
committerPatrick Georgi <pgeorgi@google.com>2020-06-22 11:51:44 +0000
commitec26428fcfb4b255d51f43597f7446f6f2f03daf (patch)
tree90b47b737ef73eb106968370e7ce8700776b4bbe /src/include
parent95b9ef2dfc3348861ca971d3f3f7e44d451ad439 (diff)
downloadcoreboot-ec26428fcfb4b255d51f43597f7446f6f2f03daf.tar.xz
soc/amd/picasso/bootblock: Write EIP to secure S3
This change is required so we have a defined entry point on S3. Without this, the S3_RESUME_EIP_MSR register could in theory be written to later which would be a security risk. BUG=b:147042464 TEST=Resume trembyle and see bootblock start. coreboot-4.12-512-g65779ebcf73f-dirty Thu Jun 4 22:38:17 UTC 2020 smm starting (log level: 8)... SMI# #6 SMI#: SLP = 0x0c01 Chrome EC: Set SMI mask to 0x0000000000000000 Chrome EC: Set SCI mask to 0x0000000000000000 Clearing pending EC events. Error code EC_RES_UNAVAILABLE(9) is expected. EC returned error result code 9 SMI#: Entering S3 (Suspend-To-RAM) PSP: Prepare to enter sleep state 3... OK SMU: Put system into S3/S4/S5 Timestamp - start of bootblock: 18446744070740509170 coreboot-4.12-512-g65779ebcf73f-dirty Thu Jun 4 22:38:17 UTC 2020 bootblock starting (log level: 8)... Family_Model: 00810f81 PMxC0 STATUS: 0x200800 SleepReset BIT11 I2C bus 3 version 0x3132322a DW I2C bus 3 at 0xfedc5000 (400 KHz) Timestamp - end of bootblock: 18446744070804450274 VBOOT: Loading verstage. FMAP: area COREBOOT found @ c75000 (3715072 bytes) CBFS: Locating 'fallback/verstage' CBFS: Found @ offset 61b80 size cee4 PROG_RUN: Setting MTRR to cache stage. base: 0x04000000, size: 0x00010000 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4b0b0d0d576fc42b1628a4547a5c9a10bcbe9d37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/include')
-rw-r--r--src/include/cpu/amd/msr.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h
index 606ea23bc0..e466e7bbf2 100644
--- a/src/include/cpu/amd/msr.h
+++ b/src/include/cpu/amd/msr.h
@@ -72,6 +72,7 @@
#define EX_CFG_MSR 0xC001102C
#define LS_CFG2_MSR 0xC001102D
#define IBS_OP_DATA3_MSR 0xC0011037
+#define S3_RESUME_EIP_MSR 0xC00110E0
#define MSR_PATCH_LEVEL 0x0000008B
#define CORE_PERF_BOOST_CTRL 0x15c