diff options
| author | Julius Werner <jwerner@chromium.org> | 2018-08-02 11:45:07 -0700 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2018-08-03 18:10:02 +0000 |
| commit | 0a0340e42e461a6e34a2e99304792f0ecac07bcb (patch) | |
| tree | d49be7f0f37c051b6aed0b80e1664ee5e0b7f80f /src/include | |
| parent | 62431a72246977a3f95257d6e791aedd020523a9 (diff) | |
| download | coreboot-0a0340e42e461a6e34a2e99304792f0ecac07bcb.tar.xz | |
gpio: Change gpio_baseX_value() function return types to unsigned
This patch changes the return type of gpio_base2_value() and related
functions from int to uint32_t. This makes more sense now that
board_id() and related functions (which are the primary use case) also
return that type. It's unlikely that we'll ever read a strapping of 32
GPIOs in a row, but if we did, we'd probably want to treat it as
unsigned.
Change-Id: I8fb7e3a7c76cb886aed40d0ada1f545180e43117
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/gpio.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/include/gpio.h b/src/include/gpio.h index 3160242562..0a37ee7087 100644 --- a/src/include/gpio.h +++ b/src/include/gpio.h @@ -29,7 +29,7 @@ void gpio_input_pulldown(gpio_t gpio); void gpio_input_pullup(gpio_t gpio); void gpio_input(gpio_t gpio); void gpio_output(gpio_t gpio, int value); -int _gpio_base3_value(const gpio_t gpio[], int num_gpio, int binary_first); +uint32_t _gpio_base3_value(const gpio_t gpio[], int num_gpio, int binary_first); /* * This function may be implemented by SoC/board code to provide @@ -60,9 +60,9 @@ uint16_t gpio_acpi_pin(gpio_t gpio); * There are also pulldown and pullup variants which default each gpio to * be configured with an internal pulldown and pullup, respectively. */ -int gpio_base2_value(const gpio_t gpio[], int num_gpio); -int gpio_pulldown_base2_value(const gpio_t gpio[], int num_gpio); -int gpio_pullup_base2_value(const gpio_t gpio[], int num_gpio); +uint32_t gpio_base2_value(const gpio_t gpio[], int num_gpio); +uint32_t gpio_pulldown_base2_value(const gpio_t gpio[], int num_gpio); +uint32_t gpio_pullup_base2_value(const gpio_t gpio[], int num_gpio); /* * Read the value presented by the set of GPIOs, when each pin is interpreted @@ -73,7 +73,7 @@ int gpio_pullup_base2_value(const gpio_t gpio[], int num_gpio); * gpio[]: pin positions to read. gpio[0] is less significant than gpio[1]. * num_gpio: number of pins to read. */ -static inline int gpio_base3_value(const gpio_t gpio[], int num_gpio) +static inline uint32_t gpio_base3_value(const gpio_t gpio[], int num_gpio) { return _gpio_base3_value(gpio, num_gpio, 0); } @@ -103,8 +103,8 @@ static inline int gpio_base3_value(const gpio_t gpio[], int num_gpio) * gpio[]: pin positions to read. gpio[0] is less significant than gpio[1]. * num_gpio: number of pins to read. */ -static inline int gpio_binary_first_base3_value(const gpio_t gpio[], - int num_gpio) +static inline uint32_t gpio_binary_first_base3_value(const gpio_t gpio[], + int num_gpio) { return _gpio_base3_value(gpio, num_gpio, 1); } |