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authorAaron Durbin <adurbin@chromium.org>2015-03-06 23:17:33 -0600
committerAaron Durbin <adurbin@chromium.org>2015-04-22 17:55:08 +0200
commitbd74a4b2d25268f7035a4478da31f27baac2aecc (patch)
tree56740c02fe396df8ccf9fc2e7401542deeebf453 /src/lib/Makefile.inc
parentcac50506238507328b8ea0f4abd458869803e6c2 (diff)
downloadcoreboot-bd74a4b2d25268f7035a4478da31f27baac2aecc.tar.xz
coreboot: common stage cache
Many chipsets were using a stage cache for reference code or when using a relocatable ramstage. Provide a common API for the chipsets to use while reducing code duplication. Change-Id: Ia36efa169fe6bd8a3dbe07bf57a9729c7edbdd46 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8625 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/lib/Makefile.inc')
-rw-r--r--src/lib/Makefile.inc9
1 files changed, 8 insertions, 1 deletions
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 5c715d7a61..043238a263 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -111,7 +111,14 @@ romstage-y += hexdump.c
romstage-$(CONFIG_REG_SCRIPT) += reg_script.c
ramstage-$(CONFIG_REG_SCRIPT) += reg_script.c
-romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += ramstage_cache.c
+ifeq ($(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM),y)
+ramstage-y += ext_stage_cache.c
+romstage-y += ext_stage_cache.c
+else
+ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
+romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
+endif
+
smm-y += cbfs.c cbfs_core.c memcmp.c
smm-$(CONFIG_COMPILER_GCC) += gcc.c