diff options
| author | Jamie Chen <jamie.chen@intel.com> | 2020-04-27 15:49:09 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-13 12:04:18 +0000 |
| commit | 92ba06fb3e6a5ba089305b6739b1b4344984ba37 (patch) | |
| tree | 40fd1caeb543978952c90f83f9df0325cb465029 /src/lib/Makefile.inc | |
| parent | 7adcfde079324b834c9a6370af38e56e34f1c45c (diff) | |
| download | coreboot-92ba06fb3e6a5ba089305b6739b1b4344984ba37.tar.xz | |
lib/spd_cache: add spd_cache common code
This patch adds some spd_cache functions. They are for implementing the
spd_cache. It's for reducing the SPD fetch time when device uses SODIMMs.
The MRC cache also includes SPD data, but there is no public header file
available to decode the struct of MRC. So SPD cache is another solution.
BUG=b:146457985
BRANCH=None
TEST=Build puff successfully and verified below two items.
one DIMM save the boot time : 158ms
two DIMM save the boot time : 265ms
Change-Id: Ia48aa022fabf8949960a50597185c9d821399522
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Diffstat (limited to 'src/lib/Makefile.inc')
| -rw-r--r-- | src/lib/Makefile.inc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 1fed543f70..b6d318e7a3 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -345,3 +345,5 @@ spd.bin-type := spd endif ramstage-y += uuid.c + +romstage-$(CONFIG_ROMSTAGE_SPD_SMBUS) += spd_cache.c |