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author | Aaron Durbin <adurbin@chromium.org> | 2015-08-04 23:59:43 -0500 |
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committer | Aaron Durbin <adurbin@chromium.org> | 2015-08-14 15:17:46 +0200 |
commit | 39bdb0bbcfebae1a7da1a51a7893541f31c4ed3d (patch) | |
tree | b869fa2d9661e51e2305bcdf2aee51f7098c4fff /src/lib/cbmem_stage_cache.c | |
parent | 75daee5ee9ae5ab81d6d74569f4a947417f30b93 (diff) | |
download | coreboot-39bdb0bbcfebae1a7da1a51a7893541f31c4ed3d.tar.xz |
intel/common: use acpi_is_wakeup_s3() in fsp_ramstage.c
acpi_is_wakeup_s3() was introduced in upstream coreboot
while the FSP support code was written. Move to using
that instead of using the romstage_handoff structure
directly.
BUG=chrome-os-partner:43636
BRANCH=None
TEST=Built, booted, suspended, and resumed on glados.
Original-Change-Id: I71601a4be3c981672e25e189c98abb6a676462bf
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290720
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I2ae4d9906e0891080481fb58b941921922a989d3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11190
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/lib/cbmem_stage_cache.c')
0 files changed, 0 insertions, 0 deletions