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| author | Vadim Bendebury <vbendeb@chromium.org> | 2015-01-09 16:55:36 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-17 09:54:12 +0200 |
| commit | 7271e23ec296b09420b72861e0d272ecbb94d2ca (patch) | |
| tree | a934ed29762bd5aa0d1ea1fef1561dfa976d3cbe /src/lib/clog2.c | |
| parent | 6cc5e52ec66585682d251f32f901c4db7b51b4d4 (diff) | |
| download | coreboot-7271e23ec296b09420b72861e0d272ecbb94d2ca.tar.xz | |
pistachio: report UART register width
Pistachio UART closely matches 8250, the only difference is that its
register file is mapped to a 32 bit bus.
Provide a function to report register with so that the Coreboot table
entry gets correct value.
BRANCH=none
BUG=chrome-os-partner:31438
TEST=with the rest of the patches integrated depthcharge console messages
show up when running on the FPGA board
Change-Id: Icd72b115b4f339800d6c8b210a6617398232f806
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e1dc4156949b20efafbca2c19ff424436a400087
Original-Change-Id: Icafb014af338e05bbf1044b791683733685ffab3
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/240028
Original-Reviewed-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9740
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/lib/clog2.c')
0 files changed, 0 insertions, 0 deletions