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author | Furquan Shaikh <furquan@google.com> | 2020-03-26 15:36:19 -0700 |
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committer | Furquan Shaikh <furquan@google.com> | 2020-04-02 16:53:55 +0000 |
commit | 5b1f335ef8aed95e01f040bc7074fb00acc8ab7e (patch) | |
tree | a119e13f3d7a88955dee92a9de23ab6973f5673e /src/lib/fit.c | |
parent | 3c57819005af59064ea0397e8b1ed59fab5a8f7c (diff) | |
download | coreboot-5b1f335ef8aed95e01f040bc7074fb00acc8ab7e.tar.xz |
soc/intel/tigerlake: Reorganize memory initialization support
This change reorganizes memory initialization code for LPDDR4x on
TGL to allow sharing of code when adding support for other memory
types. In follow-up changes, support for DDR4 will be added.
1. It adds configuration for memory topology which is currently only
MEMORY_DOWN, however DDR4 requires more topologies to be
supported.
2. spd_info structure is organized to allow mixed topologies as well.
3. DQ/DQS maps are organized to reflect hardware configuration.
TEST=Verified that volteer still boots and memory initialization is
successful.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ib625f2ab30a6e1362a310d9abb3f2051f85c3013
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/lib/fit.c')
0 files changed, 0 insertions, 0 deletions