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| author | Rizwan Qureshi <rizwan.qureshi@intel.com> | 2017-11-16 13:32:29 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-07-19 08:07:12 +0000 |
| commit | b082670234819108a15da6239e481f5c9d8b30ec (patch) | |
| tree | e83caaf80d8726e359c7b2104d1c58d77fc8b3e0 /src/lib/imd_cbmem.c | |
| parent | a302e7f46b582a163758bc9d53f8801e7cdb2443 (diff) | |
| download | coreboot-b082670234819108a15da6239e481f5c9d8b30ec.tar.xz | |
Kconfig: Add config for creating a second bootblock
Intel PCH/Southbridges have feature that it is possible
to have the southbridge/PCH look for the bootblock at a 64K or
128K/256K/512K/1MB (in case of newer SoCs) offset instead of
the usual top of flash.
Add configs to create a second bootblock and configure its size.
Change-Id: I4bbd19c35871891b762a0673f840858d972e129e
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/22533
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/lib/imd_cbmem.c')
0 files changed, 0 insertions, 0 deletions