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author | Vadim Bendebury <vbendeb@chromium.org> | 2017-10-30 18:29:03 -0700 |
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committer | Vadim Bendebury <vbendeb@chromium.org> | 2017-11-28 18:35:28 +0000 |
commit | 3b62d6b40a12ed1a882266ea725471ee0edc437c (patch) | |
tree | d0ef75535328b30aadb770925de2205fa11eeae4 /src/lib/libgcc.c | |
parent | eb72207fee10986c81d04c445c0d04cb7f130637 (diff) | |
download | coreboot-3b62d6b40a12ed1a882266ea725471ee0edc437c.tar.xz |
spi/tpm.c do not waste time on wake pulses unless necessary
The Cr50 secure chip implementation is guaranteed not to fall asleep
for 1 second after any SPI slave activity.
Let's not waste time on the wake up ping when it is not necessary.
BRANCH=cr50
BUG=b:68012381
TEST=using a protocol analyzer verified that the wake pulses are
generated only when the new coreboot stage or depthcharge start,
not on every SPI slave transaction.
Change-Id: Id8def1470ba3eab533075b9e7180f8a58e0b00b6
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/22321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/lib/libgcc.c')
0 files changed, 0 insertions, 0 deletions