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authorAngel Pons <th3fanbus@gmail.com>2020-06-21 17:42:52 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-06-27 17:28:53 +0000
commitfc7bc54e34d496a9fe2d0047eddeb9d1f48de417 (patch)
tree7eec64d2ec2e2da5477ad87c5321fc10bdb8cbbf /src/lib/memchr.c
parentf183626b225d17d1eacfa4b12ffce47e0f4d872d (diff)
downloadcoreboot-fc7bc54e34d496a9fe2d0047eddeb9d1f48de417.tar.xz
sb/intel/common: Add early SPI code
All Intel southbridges with SPI perform this write. Put it inside a function in common code. Use a different name to avoid a name clash. As it is only one statement, make it inline so that it can be defined on the header itself. It is only called once per southbridge anyway. Change-Id: I3c284d6cffd22949d50b4c4f9846ceaef38d7cda Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/lib/memchr.c')
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