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| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2019-05-03 16:08:07 +0800 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2019-05-06 15:59:55 +0000 |
| commit | 8c0acc5515f8a381cf2d33c61951d229d4ef358a (patch) | |
| tree | 7dc94eb391fd4e2a28470c67f7c6413206fbdd12 /src/lib/memchr.c | |
| parent | 1a6b5c23a1f5892c7a461d6a6ef547e2abe524f4 (diff) | |
| download | coreboot-8c0acc5515f8a381cf2d33c61951d229d4ef358a.tar.xz | |
mb/google/sarien: Fine tune SD card D3 cold timing
A13 and A15 need to set low before H12 reset. Change
the program sequence for fit HW requirement.
BUG=b:131876963
TEST=boot up and check SD card functional
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I2f1752070f24833aaaab75dea8493caf2ed7f157
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/lib/memchr.c')
0 files changed, 0 insertions, 0 deletions