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| author | Duncan Laurie <dlaurie@google.com> | 2018-12-01 16:58:52 -0800 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2018-12-04 22:49:55 +0000 |
| commit | 11340e5e1e89011f914d7f3e87bd5d9b004b2587 (patch) | |
| tree | 2f8e8200b6faa7c0fe7c16cfd666c7ff6626b494 /src/lib/timer.c | |
| parent | 221ebdc6e56ca65cb28e6069203602e52800c6f5 (diff) | |
| download | coreboot-11340e5e1e89011f914d7f3e87bd5d9b004b2587.tar.xz | |
soc/intel/cannonlake: Increase bootblock size
Increase the bootblock size to 48K to match skylake. With UART
enabled we are very near the 32K limit, and with upcoming changes
to add USB devices in devicetree for a cannonlake board it is over
the current 32K limit.
Change-Id: I155cb0a6af1746af6833fa9f35c2ea6fe0bc709f
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/lib/timer.c')
0 files changed, 0 insertions, 0 deletions