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authorDuncan Laurie <dlaurie@chromium.org>2012-04-27 10:58:22 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-05-01 21:23:32 +0200
commit4aca5d7e66178c11c15d29fb439622c93680c06c (patch)
tree986ada54eb3e314945c550b09ac6d5b222c245fb /src/lib/uart8250mem.c
parentb9fe01c881c40ea185a54b13c4ed0d604e6d36f0 (diff)
downloadcoreboot-4aca5d7e66178c11c15d29fb439622c93680c06c.tar.xz
Fix issue with PCIe power management setup
The current early PM setup that attempts to configure dynamic clock gating relies on PCIe functions to be enabled that may not be. Instead of reading port 0 or 4 directly to determine the link width use the register that refelects the soft strapping options as this will always be available. Also add a clear register assignment and break for port 0 in the switch statement instead of falling through to port 4 as that could end up setting the slot power limit based on port 4 values instead of based on port 0. register 0xE1=0x3f and all other root ports should have 0xE1=0x03. When port 0 and 4 are disabled they will have 0xE1=0x3C before being disabled by the pch enable handler. LUMPY default: 00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5) 00:1c.3 PCI bridge: Intel Corporation Device 1c16 (rev b5) pci_read8 0 0x1c 0 0xe1 0x3f pci_read8 0 0x1c 3 0xe1 0x03 LUMPY with PCIe port coalesce enabled: 00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5) 00:1c.1 PCI bridge: Intel Corporation Device 1c16 (rev b5) pci_read8 0 0x1c 0 0xe1 0x3f pci_read8 0 0x1c 1 0xe1 0x03 Change-Id: I33a37b0ec0c8e570cf5d9dda2c06e0225fee135c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/980 Tested-by: build bot (Jenkins)
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