diff options
| author | Shelley Chen <shchen@google.com> | 2020-10-06 15:50:21 -0700 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2020-10-09 19:45:40 +0000 |
| commit | afaa3d0356d5a518442701875505901e5806bb61 (patch) | |
| tree | 8cce286e32939b8141c917b1b1797a7f451b0fab /src/lib | |
| parent | 53a69507c4090633ec094173d7c03723bdbb4396 (diff) | |
| download | coreboot-afaa3d0356d5a518442701875505901e5806bb61.tar.xz | |
trogdor: Modify DDR training to use mrc_cache
Currently, trogdor devices have a section RO_DDR_TRAINING that is used
to store memory training data. Changing so that we reuse the same
mrc_cache API as x86 platforms. This requires renaming
RW_DDR_TRAINING to RW_MRC_CACHE and removing RO_DDR_TRAINING in the
fmap table.
BUG=b:150502246
BRANCH=None
TEST=FW_NAME="lazor" emerge-trogdor coreboot chromeos-bootimage
Make sure that first boot after flashing does memory training
and next boot does not.
Boot into recovery two consecutive times and make sure memory
training occurs on both boots.
Change-Id: I16d429119563707123d538738348c7c4985b7b52
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/lib')
| -rw-r--r-- | src/lib/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index ce57f51c2f..c228f2a9f4 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -100,6 +100,7 @@ ramstage-y += romstage_handoff.c romstage-y += romstage_handoff.c romstage-y += selfboot.c romstage-y += stack.c +romstage-y += rtc.c ramstage-y += rtc.c romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c |