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| author | Subrata Banik <subrata.banik@intel.com> | 2021-05-05 19:46:09 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-05-12 06:16:05 +0000 |
| commit | 8d2b0dcc4447e5189bf993f9b4854dfbd08fb55c (patch) | |
| tree | a7547d6599506e43e52621b880e3e5cc6096d537 /src/lib | |
| parent | 38e4a2d4cf3398d56640b03371ff1bd08b30aff5 (diff) | |
| download | coreboot-8d2b0dcc4447e5189bf993f9b4854dfbd08fb55c.tar.xz | |
include/console: Rename and update POST_ENTRY_RAMSTAGE postcode
Rename and update POST_ENTRY_RAMSTAGE postcode value from 0x80 to 0x6f
to make the ramstage postcodes appear in an incremental order.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I60f4bd8b2e6b2b887dee7c4991a14ce5d644fdba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/lib')
| -rw-r--r-- | src/lib/hardwaremain.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 895a942222..cd4a57e96e 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -442,7 +442,7 @@ void main(void) cbmem_initialize(); timestamp_add_now(TS_START_RAMSTAGE); - post_code(POST_ENTRY_RAMSTAGE); + post_code(POST_ENTRY_HARDWAREMAIN); /* Handoff sleep type from romstage. */ acpi_is_wakeup_s3(); |